Inventor
KUNG MORISS
TW42 patents
⚠️ This page may combine multiple inventors who share the name “KUNG MORISS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
VIA TECH INC
41 patentsUS7382049B2Jun 3, 2008
Chip package and bump connecting structure thereof
VIA TECH INC104 citations98
US6972964B2Dec 6, 2005
Module board having embedded chips and components and method of forming the same
VIA TECH INC100 citations98
US6692265B2Feb 17, 2004
Electrical connection device
VIA TECH INC81 citations98
US7176559B2Feb 13, 2007
Integrated circuit package with a balanced-part structure
VIA TECH INC113 citations94
US7180166B2Feb 20, 2007
Stacked multi-chip package
VIA TECH INC24 citations93
US7071569B2Jul 4, 2006
Electrical package capable of increasing the density of bonding pads and fine circuit lines inside a interconnection
VIA TECH INC25 citations93
US6960826B2Nov 1, 2005
Multi-chip package and manufacturing method thereof
VIA TECH INC49 citations93
US6951773B2Oct 4, 2005
Chip packaging structure and manufacturing process thereof
VIA TECH INC64 citations93
US6881662B2Apr 19, 2005
Pattern formation process for an integrated circuit substrate
VIA TECH INC20 citations93
US6865089B2Mar 8, 2005
Module board having embedded chips and components and method of forming the same
VIA TECH INC44 citations93
US6849534B2Feb 1, 2005
Process of forming bonding columns
VIA TECH INC17 citations93
US6716037B2Apr 6, 2004
Flexible electric-contact structure for IC package
VIA TECH INC23 citations93
US6707162B1Mar 16, 2004
Chip package structure
VIA TECH INC26 citations93
US6695040B1Feb 24, 2004
Thin planar heat distributor
VIA TECH INC41 citations93
US6696305B2Feb 24, 2004
Metal post manufacturing method
VIA TECH INC49 citations93
US6569712B2May 27, 2003
Structure of a ball-grid array package substrate and processes for producing thereof
VIA TECH INC45 citations90
US7101781B2Sep 5, 2006
Integrated circuit packages without solder mask and method for the same
VIA TECH INC37 citations87
US7638881B2Dec 29, 2009
Chip package
VIA TECH INC17 citations84
US7470864B2Dec 30, 2008
Multi-conducting through hole structure
VIA TECH INC14 citations84
US7342317B2Mar 11, 2008
Low coefficient of thermal expansion build-up layer packaging and method thereof
VIA TECH INC9 citations84
US7173341B2Feb 6, 2007
High performance thermally enhanced package and method of fabricating the same
VIA TECH INC10 citations84
US6916687B2Jul 12, 2005
Bump process for flip chip package
VIA TECH INC16 citations84
US6876087B2Apr 5, 2005
Chip scale package with heat dissipating part
VIA TECH INC18 citations84
US6717264B2Apr 6, 2004
High density integrated circuit package
VIA TECH INC15 citations84
US6667190B2Dec 23, 2003
Method for high layout density integrated circuit package substrate
VIA TECH INC19 citations84
US6981320B2Jan 3, 2006
Circuit board and fabricating process thereof
VIA TECH INC10 citations74
US6946727B2Sep 20, 2005
Vertical routing structure
VIA TECH INC10 citations74
US6929488B2Aug 16, 2005
Electrical connection device between a pin-typed IC package and a circuit board
VIA TECH INC7 citations74
US6902997B2Jun 7, 2005
Process of forming bonding columns
VIA TECH INC6 citations74
US6894904B2May 17, 2005
Tab package
VIA TECH INC10 citations74
US6808643B2Oct 26, 2004
Hybrid interconnect substrate and method of manufacture thereof
VIA TECH INC9 citations74
US6716692B1Apr 6, 2004
Fabrication process and structure of laminated capacitor
VIA TECH INC11 citations70
US7247951B2Jul 24, 2007
Chip carrier with oxidation protection layer
VIA TECH INC5 citations63
US7033917B2Apr 25, 2006
Packaging substrate without plating bar and a method of forming the same
VIA TECH INC4 citations63
US6849955B2Feb 1, 2005
High density integrated circuit packages and method for the same
VIA TECH INC6 citations63
US7235429B2Jun 26, 2007
Conductive block mounting process for electrical connection
VIA TECH INC0 citations52
US6896173B2May 24, 2005
Method of fabricating circuit substrate
VIA TECH INC1 citations52
US6743659B2Jun 1, 2004
Method for manufacturing multi-layer package substrates
VIA TECH INC1 citations52
US7504726B2Mar 17, 2009
Chip and manufacturing method and application thereof
VIA TECH INC0 citations51
US7622326B2Nov 24, 2009
Manufacturing process of a chip package structure
VIA TECH INC0 citations42
US6913814B2Jul 5, 2005
Lamination process and structure of high layout density substrate
VIA TECH INC0 citations42