Inventor

GARG ADESH

US20 patents

⚠️ This page may combine multiple inventors who share the name “GARG ADESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GARG ADESH

AVAGO TECH INT SALES PTE LID

Clock skew suppression for time-interleaved clocks

Digital pre-distortion method and apparatus for a digital to analog converter

Transition aware dynamic element matching

Systems for and methods of fractional frequency division

System and apparatus for on-substrate circuit configured to operate as transformer

Systems for and methods of fractional frequency division

Aging-averse bandwidth extension apparatus

System and method for transition aware binary switching for digital-to-analog converters (DACs)

BROADCOM CORP

Distributed resonate clock driver

High speed, low power all CMOS thermometer-to-binary demultiplexer

Low-power high swing CML driver with independent common-mode and swing control

Increasing output amplitude of a voltage-mode driver in a low supply voltage technology

Multilane SERDES clock and data skew alignment for multi-standard support

High speed, low power non-return-to-zero/return-to-zero output driver

High speed, low power all CMOS thermometer-to-binary demultiplexer

AVAGO TECHNOLOGIES GENERAL IP

Multiplexer circuit for a digital to analog converter

Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration

Multi-segmented all logic DAC

Multilane serdes clock and data skew alignment for multi-standard support

KHANPOUR MEHDI

Bubble correction in a flash analog-to-digital converter