Inventor

IYER JAYESH

IN17 patents

⚠️ This page may combine multiple inventors who share the name “IYER JAYESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IYER JAYESH

INTEL CORP

Hardware apparatuses and methods to fuse instructions

Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor

Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program order

Instruction and logic for predication and implicit destination

Instruction and logic for predication and implicit destination

Hardware apparatuses and methods to control access to a multiple bank data cache

Hardware apparatuses and methods to control access to a multiple bank data cache

Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator

Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor

Performing partial register write operations in a processor

Apparatus and methods to support counted loop exits in a multi-strand loop processor

Method to do control speculation on loads in a high performance strand-based loop accelerator

IYER JAYESH

Two wire serial voltage identification protocol

Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor

KRAIPAK WASEEM S

Data negotiation using serial voltage identification communication

Time negotiation using serial voltage identification communication

KOSAREV NIKOLAY

Method and apparatus for reconstructing real program order of instructions in multi-strand out-of-order processor