Inventor

LANDIS HOWARD S

US44 patents

⚠️ This page may combine multiple inventors who share the name “LANDIS HOWARD S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LANDIS HOWARD S

IBM

Planarized semiconductor structure using subminimum features

Method for planarizing semiconductor structure using subminimum features

Radial uniformity control of semiconductor wafer polishing

Method and structure of column interconnect

Method of forming borderless contacts using a removable mandrel

Planarized semiconductor structure with subminimum features

Shapes-based migration of aluminum designs to copper damascene

Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics

Stacked fill structures for support of dielectric layers

Shapes-based migration of aluminum designs to copper damascene

Trimming of dummy fill shapes holes to affect near-neighbor dummy fill shapes with built-in optical proximity corrections for semiconductor applications

Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics

Shapes-based migration of aluminum designs to copper damascence

System and method of automated wire and via layout optimization description

System and method of automated wire and via layout optimization description

Method of forming crack trapping and arrest in thin film structures

Aligned dummy metal fill and hole shapes

Method and system allowing for semiconductor design rule optimization

Low cost shallow trench isolation using non-conformal dielectric material

Circuit element function matching despite auto-generated dummy shapes

AB etch endpoint by ABFILL compensation

Modifying design layer of integrated circuit (IC)

Modifying layout of IC based on function of interconnect and related circuit and design structure

Circuit element function matching despite auto-generated dummy shapes

Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics

Stacked fill structures for support of dielectric layers

Structure for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks

Shapes-based migration of aluminum designs to copper damascene

Structure and method for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks

Shapes-based migration of aluminum designs to copper damascene

Crack trapping and arrest in thin film structures

Increased power line noise immunity in IC using capacitor structure in fill area

Modifying design layer of integrated circuit (IC) using nested and non-nested fill objects

Variable overlap of dummy shapes for improved rapid thermal anneal uniformity

Regional pattern density determination method and system

Structure and method for sub-resolution dummy clear shapes for improved gate dimensional control

LANDIS HOWARD S

Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections for semiconductor applications

Current-aligned auto-generated non-equiaxial hole shape for wiring

BICKFORD JEANNE P

Methods and systems to meet technology pattern density requirements of semiconductor fabrication processes

COLLINS DAVID S

Metal fill structures for reducing parasitic capacitance

GLOBALFOUNDRIES US INC

Wafer-scale chip structure and method and system for designing the structure

BONILLA GRISELDA

Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections

BURKHARDT MARTIN

Method of forming a semiconductor device having a cut-way hole to expose a portion of a hardmask layer

BASHABOINA PAVAN Y

Parameter variation improvement