Inventor

MILLS DUANE R

US36 patents

⚠️ This page may combine multiple inventors who share the name “MILLS DUANE R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MILLS DUANE R

MICRON TECHNOLOGY INC

Wear leveling

Techniques for sensing logic values stored in memory cells using sense amplifiers that are selectively isolated from digit lines

Memory device having 2-transistor vertical memory cell and shield structures

Memory device having 2-transistor vertical memory cell and separate read and write gates

Memory device having 2-transistor vertical memory cell and shield structures

Wear leveling

Speculative section selection within a memory device

Wear leveling

Wear leveling for random access and ferroelectric memory

Wear leveling

On-demand memory page size

Wear leveling for random access and ferroelectric memory

On demand memory page size

Wear leveling for random access and ferroelectric memory

Speculative section selection within a memory device

Memory cell sensing stress mitigation

Memory device having 2-transistor vertical memory cell and separate read and write gates

Efficient power scheme for redundancy

Techniques for sensing logic values stored in memory cells using sense amplifiers that are selectively isolated from digit lines

On demand memory page size

INTEL CORP

Synchronous interface for a nonvolatile memory

Flash memory including a mode register for indicating synchronous or asynchronous mode of operation

Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory

Asynchronous interface for a nonvolatile memory

Dynamic single bit per cell to multiple bit per cell memory

Pipelined read architecture for memory

Synchronous address latching for memory arrays

Nonvolatile memory with blocked redundant columns and corresponding content addressable memory sets

Nonvolatile memory with a programmable output of selectable width and a method for controlling the nonvolatile memory to switch between different output widths

Computer memory with status cell

Override signal for forcing a powerdown of a flash memory

Synchronous address latching for memory arrays

Method and circuitry for preventing propagation of undesired ATD pulses in a flash memory device

Pipelined read architecture for memory

Method for using an in package power supply to supply power to an integrated circuit and to a component

ABDULLA MOSTAFA NAGUIB

Wireless interface to program phase-change memories