Inventor

LAI JIIN

TW86 patents

⚠️ This page may combine multiple inventors who share the name “LAI JIIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAI JIIN

VIA TECH INC

Buffer for varying data access speed and system applying the same

Phase lock loop (PLL) clock generator with programmable skew and frequency

Memory controller for supporting a plurality of different memory accesse modes

Switching circuit capable of improving memory write timing and method thereof

Power management method of north bridge

Power management system with a bridge logic having analyzers for monitoring data quantity to modify operating clock and voltage of the processor and main memory

Apparatus and method for testing motherboard having PCI express devices

Data-maintenance method of distributed shared memory system

Delayed transaction method and device used in a PCI system

Clock generating apparatus and method thereof

Delay device having a delay lock loop and method of calibration thereof

Gated clock tree synthesis method for the logic design

Integrated testing method for concurrent testing of a number of computer components through software simulation

Data memory controller that supports data bus invert

Phase lock device and method

Processing method, chip set and controller for supporting message signaled interrupt

Method and device for signal testing

Read/write scheduling apparatus of controller chip and method for the same

Arbitration of control chipsets in bus transaction

Method and apparatus for arbitrating access to a PCI bus by a plurality of functions in a multi-function master

Method and related apparatus for accessing memory

Software-based simulation system capable of simulating the combined functionality of a north bridge test module and a south bridge test module

Memory-access management method and system for synchronous dynamic Random-Access memory or the like

Memory-access management method and system for synchronous random-access memory or the like

Method and apparatus capable of programmably delaying clock of DRAM

Non-volatile memory apparatus and address classification method thereof

PCI system controller capable of delayed transaction

Control chipset, and data transaction method and signal transmission devices therefor

Computer chip set for computer mother board referencing various clock rates

Data transmission system and method thereof

Data memory controller that supports data bus invert

Memory modules storing therein boot codes and method and device for locating same

Bridge circuit for providing conversion between PCIe-NVMe protocol and NVMe-TCP protocol and computer system using the same

Local bus with dynamic decoding capability

Method for controlling a process of writing data sent by a central processing unit to a memory by using a central processing unit interface

Computing apparatus utilizing programmable logic circuit to implement direct memory access engine and at least one physical engine and providing data to be processed to at least one physical engine through direct memory access engine

Data transmission methods and hub devices utilizing the same

Remote node accessing local memory by using distributed shared memory

Computer chip set for computer mother board referencing various clock rates

Installation for providing constant loading in memory slot

LAI JIIN

Backward compatible optical USB device

Data transmission system and method thereof

Apparatus interoperable with backward compatible optical USB device

Method and controller for power management

VIA ALLIANCE SEMICONDUCTOR CO LTD

Cache memory with unified tag and sliced data

Control system and method for cache coherency

Switch and data accessing method thereof

SHANGHAI ZHAOXIN SEMICONDUCTOR CO LTD

Microprocessor with dynamically adjustable bit width for processing data

Microprocessor for neural network computing and processing method of macroinstruction

WU CHUNG-CHE

Method and controller for power management