Inventor

SANDBERG ANDREAS LARS

GB35 patents

Patents

35 patents

US12517806B2Jan 6, 2026

Address translation circuitry and method for performing address translations based on page table level size information

ADVANCED RISC MACH LTD0 citations49

US12373350B2Jul 29, 2025

Cache-line retention hint information for conditional write instruction

ADVANCED RISC MACH LTD0 citations47

US12118101B2Oct 15, 2024

Technique for providing a trusted execution environment

ADVANCED RISC MACH LTD0 citations47

US11036639B2Jun 15, 2021

Cache apparatus and method that facilitates a reduction in energy consumption through use of first and second data arrays

ADVANCED RISC MACH LTD0 citations46

US12248409B2Mar 11, 2025

Apparatus and method of controlling access to data stored in a non-trusted memory

ADVANCED RISC MACH LTD0 citations45

US10866904B2Dec 15, 2020

Data storage for multiple data types

ADVANCED RISC MACH LTD0 citations40

US10853262B2Dec 1, 2020

Memory address translation using stored key entries

ADVANCED RISC MACH LTD0 citations40

US10761988B2Sep 1, 2020

Methods and apparatus of cache access to a data array with locality-dependent latency characteristics

ADVANCED RISC MACH LTD0 citations38

SANDBERG ANDREAS LARS

Patents

Automatic injection of weak code to attract or distract malicious actors

Branch prediction using hypervectors

System, method and apparatus for secure functions and cache line data

Performing maintenance operations

TAGE branch predictor with perceptron predictor as fallback predictor

Dynamic adjustment of memory for storing protection metadata

Parallel page table entry access when performing address translations

Delay masking action for memory access requests

Message passing circuitry and method

Apparatus and method for transferring data between address ranges in memory

Saving and restoring branch prediction state

Apparatus and method of handling caching of persistent data

Wear levelling in non-volatile memories

Cache sector usage prediction

Page table structure

Technique for managing compression of data in an apparatus

Integrity tree for memory security

Memory protection using cached partial hash values

Partial-address-translation-invalidation request

Re-encryption following an OTP update event

Apparatus and method for maintaining a counter value

Cache control in presence of speculative read operations

Address decryption for memory storage

System, method and apparatus for secure functions and cache line data

Memory address translation

Caching address translation information

Apparatus and method

Address translation circuitry and method for performing address translations based on page table level size information

Cache-line retention hint information for conditional write instruction

Technique for providing a trusted execution environment

Cache apparatus and method that facilitates a reduction in energy consumption through use of first and second data arrays

Apparatus and method of controlling access to data stored in a non-trusted memory

Data storage for multiple data types

Memory address translation using stored key entries

Methods and apparatus of cache access to a data array with locality-dependent latency characteristics