Inventor

HANAFI HUSSEIN I

US57 patents

⚠️ This page may combine multiple inventors who share the name “HANAFI HUSSEIN I”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HANAFI HUSSEIN I

IBM

Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region

Threshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power

Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process

Damascene double-gate MOSFET with vertical channel regions

Backgated FinFET having different oxide thicknesses

CMOS off-chip driver with reduced signal swing and reduced power supply disturbance

Method to control device threshold of SOI MOSFET&#39;s

Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate

Strained silicon-channel MOSFET using a damascene gate process

SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layer

Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control

Method to control device threshold of SOI MOSFET&#39;s

Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control

Method of protecting semiconductor areas while exposing a gate

Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch

Damascene double-gate MOSFET with vertical channel regions

Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme

Sacrificial silicon sidewall for damascene gate formation

Field effect transistors with improved implants and method for making such transistors

Method for making field effect transistors having sub-lithographic gates with vertical side walls

Silicon sidewall etching

Field effect transistor including damascene gate with an internal spacer structure

Nitride-encapsulated FET (NNCFET)

Method and apparatus for improving SRAM cell stability by using boosted word lines

Buried biasing wells in FETs (Field Effect Transistors)

Backgated FinFET having different oxide thicknesses

Strained silicon-channel MOSFET using a damascene gate process

Backgated FinFET having different oxide thicknesses

Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch

Damascene gate field effect transistor with an internal spacer structure

Nitride-encapsulated FET (NNCFET)

Buried biasing wells in FETS

SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layer

MICRON TECHNOLOGY INC

Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods

Distributed semiconductor device methods, apparatus, and systems

Semiconductor devices

Non-volatile SRAM cell

Back gated SRAM cell

FIN field effect transistor

Memory in logic cell

Distributed semiconductor device methods, apparatus, and systems

Back gated SRAM cell

System, apparatus, and method to increase read and write stability of scaled SRAM memory cells

Fabrication of self-aligned gallium arsenide MOSFETS using damascene gate methods

Memory cells

Methods of forming memory cells

Memory cell storage node length

FARRAR PAUL A

Distributed semiconductor device methods, apparatus, and systems

Distributed semiconductor device methods, apparatus, and systems

HANAFI HUSSEIN I

FIN field effect transistor

Method to control device threshold of SOI MOSFET's

Method to control device threshold of SOI MOSFET's