Inventor

NATZLE WESLEY

US18 patents

⚠️ This page may combine multiple inventors who share the name “NATZLE WESLEY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NATZLE WESLEY

IBM

Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region

Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process

Directional CVD process with optimized etchback

Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch

Etching of hard masks

Wafer-to-wafer control using virtual modules

Structure and method to fabricate FinFET devices

Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch

Method for cleaning the surface of a dielectric

Structure and method to fabricate finfet devices

Method of etching dual pre-doped polysilicon gate stacks using carbon-containing gaseous additions

Selective deposition of germanium spacers on nitride

TOKYO ELECTRON LTD

Formula-based run-to-run control

Dynamic metrology sampling with wafer uniformity control

Dynamic metrology sampling for a dual damascene process

Process control using physical modules and virtual modules

SIEMENS AG

Removal of post-RIE polymer on Al/Cu metal line

Removal of post-rie polymer on A1/CU metal line