Inventor

GREGORIUS PETER

DE68 patents

⚠️ This page may combine multiple inventors who share the name “GREGORIUS PETER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GREGORIUS PETER

INFINEON TECHNOLOGIES AG

Voltage regulator with a stabilization circuit for guaranteeing stabile operation

Feed forward clock and data recovery unit

Memory system and method of accessing memory chips of a memory system

Method and device for generating a clock signal using a phase difference signal and a feedback signal

Semiconductor memory chip

Method for sampling phase control

Method of reconstructing data transmitted over a transmission path in a receiver and corresponding device

High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips

High-speed interface circuit for semiconductor memory chips and memory system including the same

Method of operating a memory device, memory module, and a memory device comprising the memory module

Feed forward equalizer and a method for analog equalization of a data signal

Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals

Clock and data recovery unit

Synchronous signal generator

Memory device, memory controller and memory system having bidirectional clock lines

Device for reconstructing data from a received data signal and corresponding transceiver

Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor memory system

Overload protection circuit for line drivers

Current mode digital data transmitter

Method for measuring the delay time of a signal line

Control unit for deactivating and activating the control signals

Generating a sampling clock signal in a communication block of a memory device

Memory system with two clock lines and a memory device

Line driver for digital signal transmission

Cell array with mismatch reduction

Semiconductor memory chip

Synchronous parallel/serial converter

DB-linear variable gain amplifier (VGA) stage with a high broad band

Method and filter arrangement for digital recursive filtering in the time domain

Line driver for transmitting data

Circuit arrangement for recovering clock and data from a received signal

QIMONDA AG

Memory device and memory system comprising a memory device and a memory control device

Memory circuit

Bus termination system and method

Integrated circuit with wireless connection

High speed memory architecture

Training connections in a memory arrangement

Memory device and method of operating such

Horizontal dual in-line memory modules

Data receiver with clock recovery circuit

Circuit with selectable data paths

Data conversion

GREGORIUS PETER

Multi-port DRAM architecture for accessing different memory partitions

Method and system including plural memory controllers and a memory access control bus for accessing a memory device

INFINEON TECHNOLOGIES

Re-driving CAwD and rD signal lines

BILGER CHRISTOPH

Multi-die memory, apparatus and multi-die memory stack

RICHTER MICHAEL

Semiconductor memory with memory cell portions having different access speeds

SCHNEIDER ANDREAS

Interface voltage adjustment based on error detection

WALLNER PAUL

Semiconductor memory chip and memory system

STREIBL MARTIN

Method and device for transmitting outgoing useful signals and an outgoing clock signal