Inventor

DALTON TIMOTHY JOSEPH

US34 patents

⚠️ This page may combine multiple inventors who share the name “DALTON TIMOTHY JOSEPH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DALTON TIMOTHY JOSEPH

IBM

Method for forming a porous dielectric material layer in a semiconductor device and device formed

Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same

Wafer-to-wafer alignments

Multilayer interconnect structure containing air gaps and method for making

Dual wired integrated circuit chips

Double-sided integrated circuit chips

Semiconductor integrated circuit devices having high-Q wafer back-side capacitors

Double-sided integrated circuit chips

Semiconductor integrated circuit devices having high-Q wafer back-side capacitors

Interconnect structures and methods of making thereof

Modified via bottom structure for reliability enhancement

Multilayer interconnect structure containing air gaps and method for making

Cu/low-k BEOL with nonconcurrent hybrid dielectric interface

Low temperature Bi-CMOS compatible process for MEMS RF resonators and filters

Porous silicon composite structure as large filtration array

Deep filled vias

Diffusion barrier layer and semiconductor device containing same

Line level air gaps

Dual wired integrated circuit chips

Phase change memory element with a peripheral connection to a thin film electrode

Error detection and correction in semiconductor structures

Method of forming an interconnect structure

Dual wired integrated circuit chips

Method for forming a porous dielectric material layer in a semiconductor device and device formed

Spin-on cap layer, and semiconductor device containing same

Semiconductor recessed mask interconnect technology

Dual wired integrated circuit chips

Method for dry etching photomask material

Modified via bottom structure for reliability enhancement

Method of etching dual pre-doped polysilicon gate stacks using carbon-containing gaseous additions

Nano-scaled gate structure with self-interconnect capabilities

INFINEON TECHNOLOGIES AG

Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer

BUCHWALTER LEENA PAIVIKKI

Low temperature Bi-CMOS compatible process for MEMS RF resonators and filters

DALTON TIMOTHY JOSEPH

Structures for semiconductor structures with error detection and correction