Inventor

LA TULIPE JR DOUGLAS C

US36 patents

⚠️ This page may combine multiple inventors who share the name “LA TULIPE JR DOUGLAS C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LA TULIPE JR DOUGLAS C

IBM

Methods of forming wiring to transistor and related transistor

Substrate bonding with diffusion barrier structures

Inverted thin channel mosfet with self-aligned expanded source/drain

Advanced handler wafer bonding and debonding

Wafer bonding misalignment reduction

Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias

Reducing wafer bonding misalignment by varying thermal treatment prior to bonding

Sealed air gap for semiconductor chip

Method, system, program product for bonding two circuitry-including substrates and related stage

Method for preparing 2-dimensional semiconductor devices for integration in a third dimension

Combination of TSV and back side wiring in 3D integration

Combination of TSV and back side wiring in 3D integration

Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias

Low-cost strained SOI substrate for high-performance CMOS technology

Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias

Reducing wafer bonding misalignment by varying thermal treatment prior to bonding

Three-dimensional integrated circuit device using a wafer scale membrane

Non-relaxed embedded stressors with solid source extension regions in CMOS devices

Back end interconnect with a shaped interface

Handler wafer removal facilitated by the addition of an amorphous carbon layer on the handler wafer

INFINEON TECHNOLOGIES AG

Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer

Back end interconnect with a shaped interface

Crystallographic modification of hard mask properties

LA TULIPE JR DOUGLAS C

Edge protection of bonded wafers during wafer thinning

Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias

Wafer scale membrane for three-dimensional integrated circuit device fabrication

GLOBALFOUNDRIES INC

Substrate bonding with diffusion barrier structures

Semiconductor device with a low-K spacer and method of forming the same

BERLINER NATHANIEL C

Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness

Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness

HORAK DAVID V

Sealed air gap for semiconductor chip

BREYTA GREGORY

Semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device and a method of forming the semiconductor structure using a self-assembly approach

DORIS BRUCE B

Inverted thin channel mosfet with self-aligned expanded source/drain

CHENG KANGGUO

Non-relaxed embedded stressors with solid source extension regions in CMOS devices

KOBURGER III CHARLES WILLIAM

Field-effect-transistor with self-aligned diffusion contact

GLOBALFOUNDRIES US 2 LLC

Three-dimensional integrated circuit device fabrication including wafer scale membrane