Inventor

WANG YUN-YU

US96 patents

⚠️ This page may combine multiple inventors who share the name “WANG YUN-YU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG YUN-YU

IBM

Method for forming metal replacement gate of high performance

Method and structure for controlling the interface roughness of cobalt disilicide

Method for self-aligned formation of silicide contacts using metal silicon alloys for limited silicon consumption and for reduction of bridging

Interconnect structure having enhanced electromigration reliability and a method of fabricating same

Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer

Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer

Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy

Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy

Method for forming an atomically flat interface for a highly disordered metal-silicon barrier film

HDP-based ILD capping layer

Capping layer for improved silicide formation in narrow semiconductor structures

Plasma treatment to enhance inorganic dielectric adhesion to copper

High dielectric constant material deposition to achieve high capacitance

Conversion of amorphous layer produced during IMP Ti deposition

Pre-anneal of CoSi, to prevent formation of amorphous layer between Ti-O-N and CoSi

3D transistor channel mobility enhancement

Reducing dislocation formation in semiconductor devices through targeted carbon implantation

Metal cap for interconnect structures

Method of forming an interconnect including a dielectric cap having a tensile stress

Methods for forming CMOS devices with intrinsically stressed metal silicide layers

Chromium adhesion layer for copper vias in low-k technology

Copper vias in low-k technology

Microstructure liner having improved adhesion

Capacitor stack structure and method of fabricating description

Method for improved fabrication of salicide structures

Method for reducing dendrite formation in nickel silicon salicide processes

Electron holography method

Flat interface for a metal-silicon contract barrier film

3D transistor channel mobility enhancement

Method to generate porous organic dielectric

Structure for controlling the interface roughness of cobalt disilicide

Site-specific methodology for localization and analyzing junction defects in mosfet devices

Quantum conductive recrystallization barrier layers

Flat interface for a metal-silicon contact barrier film

Structure to improve adhesion between top CVD low-K dielectric and dielectric capping layer

Compressive nitride film and method of manufacturing thereof

HDP-based ILD capping layer

Ti liner for copper interconnect with low-k dielectric

Plasma treatment to enhance inorganic dielectric adhesion to copper

INFINEON TECHNOLOGIES AG

Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer

Back end interconnect with a shaped interface

Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof

Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof

GLOBALFOUNDRIES INC

Generating tensile strain in bulk finFET channel

Method of producing an un-distorted dark field strain map at high spatial resolution through dark field electron holography

Liner replacements for interconnect openings

YANG CHIH-CHAO

Interconnect structure having enhanced electromigration reliability and a method of fabricating same

ST MICROELECTRONICS INC

Copper seed layer for an interconnect structure having a doping concentration level gradient

DOMENICUCCI ANTHONY G

Method of fabricating a device using low temperature anneal processes, a device and design structure

CHAN KEVIN K

Method of replacement source/drain for 3D CMOS transistors