Inventor
SU CHAO-YUAN
TW32 patents
⚠️ This page may combine multiple inventors who share the name “SU CHAO-YUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
25 patentsUS6743660B2Jun 1, 2004
Method of making a wafer level chip scale package
TAIWAN SEMICONDUCTOR MFG110 citations97
US6756294B1Jun 29, 2004
Method for improving bump reliability for flip chip devices
TAIWAN SEMICONDUCTOR MFG53 citations96
US7892962B2Feb 22, 2011
Nail-shaped pillar for wafer-level chip-scale packaging
TAIWAN SEMICONDUCTOR MFG20 citations92
US7825517B2Nov 2, 2010
Method for packaging semiconductor dies having through-silicon vias
TAIWAN SEMICONDUCTOR MFG20 citations92
US7294937B2Nov 13, 2007
Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
TAIWAN SEMICONDUCTOR MFG26 citations92
US7126225B2Oct 24, 2006
Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
TAIWAN SEMICONDUCTOR MFG29 citations92
US6636313B2Oct 21, 2003
Method of measuring photoresist and bump misalignment
TAIWAN SEMICONDUCTOR MFG37 citations92
US6602775B1Aug 5, 2003
Method to improve reliability for flip-chip device for limiting pad design
TAIWAN SEMICONDUCTOR MFG29 citations92
US7105920B2Sep 12, 2006
Substrate design to improve chip package reliability
TAIWAN SEMICONDUCTOR MFG23 citations91
US7157734B2Jan 2, 2007
Semiconductor bond pad structures and methods of manufacturing thereof
TAIWAN SEMICONDUCTOR MFG23 citations87
US6805279B2Oct 19, 2004
Fluxless bumping process using ions
TAIWAN SEMICONDUCTOR MFG28 citations86
US6974659B2Dec 13, 2005
Method of forming a solder ball using a thermally stable resinous protective layer
TAIWAN SEMICONDUCTOR MFG15 citations84
US6770510B1Aug 3, 2004
Flip chip process of flux-less no-flow underfill
TAIWAN SEMICONDUCTOR MFG13 citations84
US6715524B2Apr 6, 2004
DFR laminating and film removing system
TAIWAN SEMICONDUCTOR MFG16 citations82
US7075016B2Jul 11, 2006
Underfilling efficiency by modifying the substrate design of flip chips
TAIWAN SEMICONDUCTOR MFG8 citations74
US6821813B2Nov 23, 2004
Process for bonding solder bumps to a substrate
TAIWAN SEMICONDUCTOR MFG11 citations74
US7276454B2Oct 2, 2007
Application of impressed-current cathodic protection to prevent metal corrosion and oxidation
TAIWAN SEMICONDUCTOR MFG5 citations73
US7134199B2Nov 14, 2006
Fluxless bumping process
TAIWAN SEMICONDUCTOR MFG10 citations73
US8829653B2Sep 9, 2014
Exclusion zone for stress-sensitive circuit design
TAIWAN SEMICONDUCTOR MFG2 citations63
US7256071B2Aug 14, 2007
Underfilling efficiency by modifying the substrate design of flip chips
TAIWAN SEMICONDUCTOR MFG5 citations63
US7906425B2Mar 15, 2011
Fluxless bumping process
TAIWAN SEMICONDUCTOR MFG4 citations62
US7468321B2Dec 23, 2008
Application of impressed-current cathodic protection to prevent metal corrosion and oxidation
TAIWAN SEMICONDUCTOR MFG4 citations62
US7154185B2Dec 26, 2006
Encapsulation method for SBGA
TAIWAN SEMICONDUCTOR MFG6 citations60
US7098082B2Aug 29, 2006
Microelectronics package assembly tool and method of manufacture therewith
TAIWAN SEMICONDUCTOR MFG0 citations52
US6802250B2Oct 12, 2004
Stencil design for solder paste printing
TAIWAN SEMICONDUCTOR MFG1 citations52
SU CHAO-YUAN
3 patentsUS8624346B2Jan 7, 2014
Exclusion zone for stress-sensitive circuit design
SU CHAO-YUAN4 citations82
US8124458B2Feb 28, 2012
Method for packaging semiconductor dies having through-silicon vias
SU CHAO-YUAN3 citations61
US8629563B2Jan 14, 2014
Method for packaging semiconductor dies having through-silicon vias
SU CHAO-YUAN0 citations51