Inventor

KONIGSFELD KRIS G

US24 patents

⚠️ This page may combine multiple inventors who share the name “KONIGSFELD KRIS G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KONIGSFELD KRIS G

INTEL CORP

Method and apparatus for blocking execution of and storing load operations during their execution

Method and apparatus for blocking execution of and storing load operations during their execution

Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers

Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system

Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system

Apparatus and method for maintaining processing consistency in a computer system having multiple processors

Method and apparatus for performing operations based upon the addresses of microinstructions

Method and apparatus for dispatching and executing a load operation to memory

Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system

Method and apparatus for performing a store operation

Apparatus for indicating an oldest non-retired load operation in an array

Method and apparatus for calculating effective memory addresses

Method and apparatus for performing multiple load operations to the same memory location in a computer system

Method and apparatus for performing floating point to integer transfers and vice versa

Method and apparatus for disabling interrupts in a highly pipelined processor

Computer system that maintains processor ordering consistency by snooping an external bus for conflicts during out of order execution of memory access instructions

Method and apparatus for handling code segment violations in a computer system

Method and apparatus for determining the dispatch readiness of buffered load operations in a processor

Method and apparatus for performing load operations in a computer system

Method and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered store

Method and apparatus for saving the effective address of floating point memory operations in an out-of-order microprocessor

Method and apparatus for executing and dispatching store operations in a computer system

(unassigned)

Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations

INTEL CORPORAITON

Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers