Inventor
MADLAND PAUL D
US23 patents
⚠️ This page may combine multiple inventors who share the name “MADLAND PAUL D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
21 patentsUS5881262AMar 9, 1999
Method and apparatus for blocking execution of and storing load operations during their execution
INTEL CORP126 citations98
US5526510AJun 11, 1996
Method and apparatus for implementing a single clock cycle line replacement in a data cache unit
INTEL CORP157 citations97
US5724536AMar 3, 1998
Method and apparatus for blocking execution of and storing load operations during their execution
INTEL CORP74 citations96
US5680572AOct 21, 1997
Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers
INTEL CORP58 citations96
US5606670AFeb 25, 1997
Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system
INTEL CORP80 citations96
US5577200ANov 19, 1996
Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system
INTEL CORP80 citations96
US5532636AJul 2, 1996
Source-switched charge pump circuit
INTEL CORP64 citations96
US5018111AMay 21, 1991
Timing circuit for memory employing reset function
INTEL CORP79 citations96
US5717882AFeb 10, 1998
Method and apparatus for dispatching and executing a load operation to memory
INTEL CORP37 citations93
US5588126ADec 24, 1996
Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system
INTEL CORP36 citations93
US6378062B1Apr 23, 2002
Method and apparatus for performing a store operation
INTEL CORP32 citations92
US5860154AJan 12, 1999
Method and apparatus for calculating effective memory addresses
INTEL CORP39 citations92
US5826109AOct 20, 1998
Method and apparatus for performing multiple load operations to the same memory location in a computer system
INTEL CORP49 citations92
US5748937AMay 5, 1998
Computer system that maintains processor ordering consistency by snooping an external bus for conflicts during out of order execution of memory access instructions
INTEL CORP47 citations92
US5694574ADec 2, 1997
Method and apparatus for performing load operations in a computer system
INTEL CORP48 citations92
US5434987AJul 18, 1995
Method and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered store
INTEL CORP33 citations92
US4926387AMay 15, 1990
Memory timing circuit employing scaled-down models of bit lines using reduced number of memory cells
INTEL CORP31 citations92
US5664137ASep 2, 1997
Method and apparatus for executing and dispatching store operations in a computer system
INTEL CORP52 citations90
US6377078B1Apr 23, 2002
Circuit to reduce charge sharing for domino circuits with pulsed clocks
INTEL CORP8 citations74
US4727518AFeb 23, 1988
Apparatus for limiting minority carrier injection in CMOS memories
INTEL CORP7 citations74
US5844852ADec 1, 1998
Memory arrays with integrated bit line voltage stabilization circuitry
INTEL CORP0 citations52