Inventor

LU LEE-CHUNG

TW192 patents

⚠️ This page may combine multiple inventors who share the name “LU LEE-CHUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LU LEE-CHUNG

TAIWAN SEMICONDUCTOR MFG CO LTD

Flip-flop with delineated layout for reduced footprint

Semiconductor device including standard cells having different cell height

Integrated circuit and method of forming an integrated circuit

Integrated circuit and method of forming an integrated circuit

Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same

Low-power flip-flop architecture with high-speed transmission gates

Semiconductor device and method of manufacturing the same

Method for generating layout diagram including cell having pin patterns and semiconductor device based on same

Semiconductor device including standard cells

Double height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same

Integrated circuit layout method and device

Integrated circuit, system for and method of forming an integrated circuit

Cell of transmission gate free circuit and integrated circuit layout including the same

Method and system of expanding set of standard cells which comprise a library

Flip-flop with delineated layout for reduced footprint

Flip-flop with delineated layout for reduced footprint

Internal clock gated cell

Flip flop circuit

Non-hierarchical metal layers for integrated circuits

Flip-flop device and method of operating flip-flop device

Semiconductor structure

Integrated circuit having a high cell density

TAIWAN SEMICONDUCTOR MFG

Dummy pattern design for reducing device performance drift

Masks formed based on integrated circuit layout design having standard cell that includes extended active region

Standard cell without OD space effect in Y-direction

Method for using mixed multi-Vt devices in a cell-based design

Method of using mixed multi-Vt devices in a cell-based design

De-coupling capacitors produced by utilizing dummy conductive structures integrated circuits

Methodology to optimize hierarchical clock skew by clock delay compensation

Layout architecture for improving circuit performance

Method and apparatus to perform resistance and capacitance (RC) parameter customization for better timing closure results in physical synthesis and optimization

Methodology of generating antenna effect models for library/IP in VLSI physical design

Flip-flop circuit

Masks formed based on integrated circuit layout design having cell that includes extended active region

Integrated circuit

Multiple via connections using connectivity rings

Flexible routing channels among vias

Self-aligned multiple patterning layout design

LU LEE-CHUNG

Non-hierarchical metal layers for integrated circuits

Methods for cell boundary isolation in double patterning design

Mask-shift-aware RC extraction for double patterning design

System and method for on-chip-variation analysis

CHEN HUANG-YU

Cell layout for multiple patterning technology

Routing system and method for double patterning technology

Method and apparatus for achieving multiple patterning technology compliant design layout

HOU YUNG-CHIN

Standard cells having flexible layout architecture/boundaries

Integrated circuit design using DFM-enhanced architecture

CHENG YI-KAN

Routing method for double patterning design

DHONG SANG HOO

Planar compatible FDSOI design architecture

HSU CHIN-CHANG

Decomposition and marking of semiconductor device design layout in double patterning lithography