Inventor
UHLMANN GREGORY JOHN
US25 patents
Patents
25 patentsUS6498057B1Dec 24, 2002
Method for implementing SOI transistor source connections using buried dual rail distribution
IBM47 citations96
US5778243AJul 7, 1998
Multi-threaded cell for a memory
IBM211 citations96
US6629236B1Sep 30, 2003
Master-slave latch circuit for multithreaded processing
IBM74 citations95
US6895215B2May 17, 2005
Method and apparatus for transferring correspondence information
IBM35 citations92
US6670716B2Dec 30, 2003
Silicon-on-insulator (SOI) semiconductor structure for implementing transistor source connections using buried dual rail distribution
IBM34 citations92
US6211713B1Apr 3, 2001
Adjustable feedback for CMOS latches
IBM33 citations92
US6060909AMay 9, 2000
Compound domino logic circuit including an output driver section with a latch
IBM24 citations92
US7224633B1May 29, 2007
eFuse sense circuit
IBM49 citations90
US7088994B2Aug 8, 2006
Network address lookup for telephony devices
IBM14 citations84
US6163173ADec 19, 2000
Method and apparatus for implementing adjustable logic threshold in dynamic circuits for maximizing circuit performance
IBM19 citations84
US7528646B2May 5, 2009
Electrically programmable fuse sense circuit
IBM14 citations83
US7725844B2May 25, 2010
Method and circuit for implementing eFuse sense amplifier verification
IBM10 citations82
US7514276B1Apr 7, 2009
Aligning stacked chips using resistance assistance
IBM12 citations75
US7489572B2Feb 10, 2009
Method for implementing eFuse sense amplifier testing without blowing the eFuse
IBM6 citations73
US7689950B2Mar 30, 2010
Implementing Efuse sense amplifier testing without blowing the Efuse
IBM3 citations62
US7532057B2May 12, 2009
Electrically programmable fuse sense circuit
IBM4 citations62
US6084810AJul 4, 2000
Dynamic logic circuit with bitline repeater circuit
IBM4 citations62
US7764531B2Jul 27, 2010
Implementing precise resistance measurement for 2D array efuse bit cell using differential sense amplifier, balanced bitlines, and programmable reference resistor
IBM5 citations61
US7729188B2Jun 1, 2010
Method and circuit for implementing enhanced eFuse sense circuit
IBM5 citations60
US6928009B2Aug 9, 2005
Redundancy circuit for memory array and method for disabling non-redundant wordlines and for enabling redundant wordlines
IBM0 citations52
US7733722B2Jun 8, 2010
Apparatus for implementing eFuse sense amplifier testing without blowing the eFuse
IBM1 citations51
US6266800B1Jul 24, 2001
System and method for eliminating effects of parasitic bipolar transistor action in dynamic logic using setup time determination
IBM1 citations51
US5973971AOct 26, 1999
Device and method for verifying independent reads and writes in a memory array
IBM0 citations51
US7865859B2Jan 4, 2011
Implementing APS voltage level activation with secondary chip in stacked-chip technology
IBM0 citations41
US7203518B2Apr 10, 2007
Method and apparatus for simplified data dispensation to and from digital systems
IBM0 citations40