Inventor
PANG RAYMOND C
US34 patents
⚠️ This page may combine multiple inventors who share the name “PANG RAYMOND C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
33 patentsUS7117373B1Oct 3, 2006
Bitstream for configuring a PLD with encrypted design data
XILINX INC65 citations98
US6931543B1Aug 16, 2005
Programmable logic device with decryption algorithm and decryption key
XILINX INC114 citations98
US6441641B1Aug 27, 2002
Programmable logic device with partial battery backup
XILINX INC113 citations98
US6373779B1Apr 16, 2002
Block RAM having multiple configurable write modes for use in a field programmable gate array
XILINX INC91 citations98
US6366117B1Apr 2, 2002
Nonvolatile/battery-backed key in PLD
XILINX INC126 citations98
US7058177B1Jun 6, 2006
Partially encrypted bitstream method
XILINX INC71 citations97
US6120551ASep 19, 2000
Hardwire logic device emulating an FPGA
XILINX INC88 citations97
US7710813B1May 4, 2010
Electronic fuse array
XILINX INC73 citations96
US7117372B1Oct 3, 2006
Programmable logic device with decryption and structure for preventing design relocation
XILINX INC56 citations96
US6981153B1Dec 27, 2005
Programmable logic device with method of preventing readback
XILINX INC53 citations96
US6965675B1Nov 15, 2005
Structure and method for loading encryption keys through a test access port
XILINX INC55 citations96
US6957340B1Oct 18, 2005
Encryption key for multi-key encryption in programmable logic device
XILINX INC54 citations96
US6346825B1Feb 12, 2002
Block RAM with configurable data width and parity for use in a field programmable gate array
XILINX INC29 citations93
US7501879B1Mar 10, 2009
eFuse resistance sensing scheme with improved accuracy
XILINX INC21 citations92
US7402443B1Jul 22, 2008
Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes
XILINX INC20 citations92
US7046052B1May 16, 2006
Phase matched clock divider
XILINX INC25 citations92
US6664837B1Dec 16, 2003
Delay line trim unit having consistent performance under varying process and temperature conditions
XILINX INC46 citations92
US6353921B1Mar 5, 2002
Hardwire logic device emulating any of two or more FPGAs
XILINX INC15 citations92
US5991908ANov 23, 1999
Boundary scan chain with dedicated programmable routing
XILINX INC39 citations92
US7345507B1Mar 18, 2008
Multi-product die configurable as two or more programmable integrated circuits of different logic capacities
XILINX INC27 citations91
US7515452B1Apr 7, 2009
Interleaved memory cell with single-event-upset tolerance
XILINX INC23 citations90
US7598749B1Oct 6, 2009
Integrated circuit with fuse programming damage detection
XILINX INC12 citations83
US7491576B1Feb 17, 2009
Yield-enhancing methods of providing a family of scaled integrated circuits
XILINX INC10 citations82
US7157951B1Jan 2, 2007
Digital clock manager capacitive trim unit
XILINX INC16 citations82
US7638822B1Dec 29, 2009
Memory cell with single-event-upset tolerance
XILINX INC14 citations81
US7248491B1Jul 24, 2007
Circuit for and method of implementing a content addressable memory in a programmable logic device
XILINX INC8 citations74
US7242633B1Jul 10, 2007
Memory device and method of transferring data in memory device
XILINX INC7 citations74
US6282127B1Aug 28, 2001
Block RAM with reset to user selected value
XILINX INC11 citations74
US6134517AOct 17, 2000
Method of implementing a boundary scan chain
XILINX INC10 citations73
US7038519B1May 2, 2006
Digital clock manager having cascade voltage switch logic clock paths
XILINX INC5 citations63
US6897676B1May 24, 2005
Configuration enable bits for PLD configurable blocks
XILINX INC3 citations63
US7451369B1Nov 11, 2008
Scalable columnar boundary scan architecture for integrated circuits
XILINX INC4 citations62
US7535278B1May 19, 2009
Circuits and methods of using parallel counter controlled delay lines to generate a clock signal
XILINX INC5 citations61