Inventor

DIRKS JUERGEN

DE25 patents

⚠️ This page may combine multiple inventors who share the name “DIRKS JUERGEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DIRKS JUERGEN

LSI CORP

Timing violation debugging inside place and route tool

On-chip scan clock generator for ASIC testing

Advanced standard cell power connection

On-the-fly RTL instructor for advanced DFT and design closure

Optimization of flip flop initialization structures with respect to design size and design closure effort from RTL to netlist

Intelligent timing analysis and constraint generation GUI

Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage

Method and computer program for configuring an integrated circuit design for static timing analysis

Intelligent timing analysis and constraint generation GUI

Special engineering change order cells

LSI LOGIC CORP

Timing violation debugging inside place and route tool

Engineering change order scenario manager

Special tie-high/low cells for single metal layer route changes

Optimized buffering for JTAG boundary scan nets

Cell builder for different layer stacks

Placement of a clock signal supply network during design of integrated circuits

DIRKS JUERGEN

Intelligent timing analysis and constraint generation GUI

Generating integrated circuit floorplan layouts

Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage

Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage

Special engineering change order cells

Method and system for controlling a turbocompressor group

DINTER MATTHIAS

Timing violation debugging inside place and route tool

KROENKE CHRISTIAN

Method and system for eliminating implementation timing in synchronization circuits

BLOCK STEFAN

Clock tree insertion delay independent interface