P

Inventor

CHIANG WEN-CHUAN

TW49 patents
⚠️ This page may combine multiple inventors who share the name “CHIANG WEN-CHUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAIWAN SEMICONDUCTOR MFG

34 patents
US7564105B2Jul 21, 2009

Quasi-plannar and FinFET-like transistors on bulk silicon

TAIWAN SEMICONDUCTOR MFG138 citations98
US6143604ANov 7, 2000

Method for fabricating small-size two-step contacts for word-line strapping on dynamic random access memory (DRAM)

TAIWAN SEMICONDUCTOR MFG252 citations98
US6080637AJun 27, 2000

Shallow trench isolation technology to eliminate a kink effect

TAIWAN SEMICONDUCTOR MFG88 citations98
US6168984B1Jan 2, 2001

Reduction of the aspect ratio of deep contact holes for embedded DRAM devices

TAIWAN SEMICONDUCTOR MFG61 citations96
US6420226B1Jul 16, 2002

Method of defining a buried stack capacitor structure for a one transistor RAM cell

TAIWAN SEMICONDUCTOR MFG38 citations93
US6271125B1Aug 7, 2001

Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure

TAIWAN SEMICONDUCTOR MFG42 citations93
US6194234B1Feb 27, 2001

Method to evaluate hemisperical grain (HSG) polysilicon surface

TAIWAN SEMICONDUCTOR MFG23 citations93
US6177340B1Jan 23, 2001

Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure

TAIWAN SEMICONDUCTOR MFG39 citations93
US6165839ADec 26, 2000

Process to fabricate a cylindrical, capacitor structure under a bit line structure for a dynamic random access memory cell

TAIWAN SEMICONDUCTOR MFG53 citations93
US6103455AAug 15, 2000

Method to form a recess free deep contact

TAIWAN SEMICONDUCTOR MFG22 citations93
US5968278AOct 19, 1999

High aspect ratio contact

TAIWAN SEMICONDUCTOR MFG19 citations93
US6638813B1Oct 28, 2003

Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell

TAIWAN SEMICONDUCTOR MFG33 citations92
US6403416B1Jun 11, 2002

Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM)

TAIWAN SEMICONDUCTOR MFG29 citations92
US6287939B1Sep 11, 2001

Method for fabricating a shallow trench isolation which is not susceptible to buried contact trench formation

TAIWAN SEMICONDUCTOR MFG25 citations92
US6214715B1Apr 10, 2001

Method for fabricating a self aligned contact which eliminates the key hole problem using a two step spacer deposition

TAIWAN SEMICONDUCTOR MFG37 citations92
US6168989B1Jan 2, 2001

Process for making new and improved crown-shaped capacitors on dynamic random access memory cells

TAIWAN SEMICONDUCTOR MFG33 citations92
US5922515AJul 13, 1999

Approaches to integrate the deep contact module

TAIWAN SEMICONDUCTOR MFG20 citations92
US7091543B2Aug 15, 2006

Embedded dual-port DRAM process

TAIWAN SEMICONDUCTOR MFG38 citations91
US6661043B1Dec 9, 2003

One-transistor RAM approach for high density memory application

TAIWAN SEMICONDUCTOR MFG27 citations89
US6227211B1May 8, 2001

Uniformity improvement of high aspect ratio contact by stop layer

TAIWAN SEMICONDUCTOR MFG23 citations87
US8759193B2Jun 24, 2014

Method of fabricating semiconductor device

TAIWAN SEMICONDUCTOR MFG6 citations84
US6187659B1Feb 13, 2001

Node process integration technology to improve data retention for logic based embedded dram

TAIWAN SEMICONDUCTOR MFG17 citations84
US7994040B2Aug 9, 2011

Semiconductor device and fabrication thereof

TAIWAN SEMICONDUCTOR MFG11 citations80
US6376294B1Apr 23, 2002

Method to define poly dog-bone for word line strapping contact at stitch area in embedded DRAM process

TAIWAN SEMICONDUCTOR MFG10 citations74
US6174802B1Jan 16, 2001

Method for fabricating a self aligned contact which eliminates the key hole problem using a two step contact deposition

TAIWAN SEMICONDUCTOR MFG7 citations74
US6020236AFeb 1, 2000

Method to form capacitance node contacts with improved isolation in a DRAM process

TAIWAN SEMICONDUCTOR MFG15 citations74
US9269760B2Feb 23, 2016

Method of fabricating semiconductor device

TAIWAN SEMICONDUCTOR MFG3 citations73
US6794254B1Sep 21, 2004

Embedded dual-port DRAM process

TAIWAN SEMICONDUCTOR MFG10 citations72
US8969937B2Mar 3, 2015

Semiconductor device

TAIWAN SEMICONDUCTOR MFG3 citations63
US6235580B1May 22, 2001

Process for forming a crown shaped capacitor structure for a DRAM device

TAIWAN SEMICONDUCTOR MFG6 citations63
US7633110B2Dec 15, 2009

Memory cell

TAIWAN SEMICONDUCTOR MFG6 citations62
US7371634B2May 13, 2008

Amorphous carbon contact film for contact hole etch process

TAIWAN SEMICONDUCTOR MFG5 citations62
US6306767B1Oct 23, 2001

Self-aligned etching method for forming high areal density patterned microelectronic structures

TAIWAN SEMICONDUCTOR MFG2 citations62
US7482278B1Jan 27, 2009

Key-hole free process for high aspect ratio gap filling with reentrant spacer

TAIWAN SEMICONDUCTOR MFG2 citations60

TAIWAN SEMICONDUCTOR MFG CO LTD

10 patents

TU KUO-CHI

2 patents

CHI MIN-HWA

1 patent

PAI CHIH-YANG

1 patent

CHEN KUO-JI

1 patent