Inventor

CHAKRADHAR SRIMAT T

US50 patents

⚠️ This page may combine multiple inventors who share the name “CHAKRADHAR SRIMAT T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAKRADHAR SRIMAT T

NEC LAB AMERICA INC

Content-based information retrieval architecture

Method for generating, from a test cube set, a generator configured to generate a test pattern

Method and apparatus for testing logic circuit designs

Storage-efficient and collision-free hash-based packet processing architecture and method

Test output compaction with improved blocking of unknown values

Externally-loaded weighted random test pattern compression

Restricted scan reordering technique to enhance delay fault coverage

Method and apparatus for testing logic circuit designs

Test output compaction using response shaper

Automatic pipelining framework for heterogeneous parallel computing systems

Method and apparatus for structured ASIC test point insertion

Hybrid scan-based delay testing technique for compact and high fault coverage test set

Test pattern compression with pattern-independent design-independent seed compression

Compiler-guided software accelerator for iterative HADOOP® jobs

System and method for parallelizing and accelerating learning machine training and classification using a massively parallel accelerator

Method for simultaneous scheduling of processes and offloading computation on many-core coprocessors

Method for blocking unknown values in output response of scan test patterns for testing circuits

Automatically boosting the software content of system LSI designs

Test output compaction for responses with unknown values

Method and system usable in sensor networks for handling memory faults

Information retrieval architecture for packet classification

NEC USA INC

Method and apparatus for efficient register-transfer level (RTL) power estimation

Segmented compaction with pruning and critical fault elimination

Process for dynamic composition and test cycles reduction

Redesign of sequential circuits to reduce clock period

Optimal retiming of synchronous logic circuits

Static test sequence compaction using two-phase restoration and segment manipulation

Testing and removal of redundancies in VLSI circuits with non-boolean primitives

Selection of partial scan flip-flops to break feedback cycles

Method for testing asynchronous circuits

Initializable asynchronous circuit design

Deriving signal constraints to accelerate sequential test generation

VLSI circuits designed for testability and methods for producing them

Identification and test generation for primitive faults

Resynthesis and retiming for optimum partial scan testing

Vector restoration using accelerated validation and refinement

Method for synthesizing a sequential circuit

Testing VLSI circuits for defects

Test generation of sequential circuits using software transformations

On-line partitioning for sequential circuit test generation

NEC CORP

Power mode based macro-models for power estimation of electronic circuits

Re-configurable embedded core test protocol for system-on-chips (SOC) and circuit boards

BECCHI MICHELA

Method and system for memory aware runtime to support multitenancy in heterogeneous clusters

Method and system to dynamically bind and unbind applications on a general purpose graphics processing unit

UNIV CALIFORNIA

System and method for testing high speed VLSI devices using slower testers

RAVI NISHKAM

Computer-guided holistic optimization of MapReduce applications

LI CHENG-HONG

Interference-driven resource management for GPU-based heterogeneous clusters

MAJUMDAR ABHINANDAN

Energy efficient heterogeneous systems

CHAKRADHAR SRIMAT T

Methods and systems for managing computations on a hybrid computing platform including a parallel accelerator

WU HAICHENG

Optimizing data warehousing applications for GPUs using dynamic stream scheduling and dispatch of fused and split kernels