Inventor
KARKHANIS TEJAS S
US4 patents
⚠️ This page may combine multiple inventors who share the name “KARKHANIS TEJAS S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
2 patentsUS7249331B2Jul 24, 2007
Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores
IBM8 citations71
US7818696B2Oct 19, 2010
Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores
IBM1 citations50