Inventor

SESHADRI ANAND

US35 patents

⚠️ This page may combine multiple inventors who share the name “SESHADRI ANAND”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SESHADRI ANAND

TEXAS INSTRUMENTS INC

Method and apparatus to reduce storage node disturbance in ferroelectric memory

Local interconnect using the electrode of a ferroelectric

Non-volatile SRAM

SRAM well-tie with an uninterrupted grated first poly and first contact patterns in a bit cell array

Method and apparatus for protecting gate oxide from process-induced charging effects

Delay system for generating control signals in ferroelectric memory devices

Mid-cycle adjustment of internal clock signal timing

Accelerated low power fatigue testing of FRAM

Ferroelectric memory reference generator systems using staging capacitors

Depletion mode MOS capacitor with patterned VT implants

Depletion mode MOS capacitor with patterned Vt implants

Read-current and word line delay path tracking for sense amplifier enable timing

SRAM cell having an N-well bias

Re-programmable integrated circuit architecture and method of manufacture

Transistor layout for manufacturing process control

Method to fabricate a self aligned source resistor in embedded flash memory applications

Array-based integrated circuit with reduced proximity effects

SRAM cell for single sided write

Redundancy arrangement for novel memory architecture

eFUSE programming feedback circuits and methods

SRAM well-tie with an uninterrupted grated first poly and first contact patterns in a bit cell array

SESHADRI ANAND

Retain-till-accessed power saving mode in high-performance static memories

Reduced power consumption in retain-till-accessed static memories

Method of screening static random access memory cells for positive bias temperature instability

Low power retention random access memory with error correction on wake-up

Asymmetric SRAM cell with split transistors on the strong side

SRAM cell having an n-well bias

SRAM cell having a p-well bias

HOUSTON THEODORE W

6T SRAM cell with single sided write

SRAM cell for single sided write

DENG XIAOWEI

Static random access memory cell with single-sided buffer and asymmetric construction

Array-based integrated circuit with reduced proximity effects

PARIKH ASHESH

Transistor layout for manufacturing process control

HERAGU KEERTHINARAYAN P

Apparatus and method for accelerating simulations and designing integrated circuits and other systems

STATE STREET BANK AND TRUST COMPANY

Use of artificial intelligence techniques to identify possible inadvertent data disclosures in emails