Inventor

SAENGER KATHERINE L

US100 patents

⚠️ This page may combine multiple inventors who share the name “SAENGER KATHERINE L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAENGER KATHERINE L

IBM

In-situ endpoint detection and process monitoring method and apparatus for chemical-mechanical polishing

Mixed orientation and mixed material semiconductor-on-insulator wafer

Hybrid orientation substrates by in-place bonding and amorphization/templated recrystallization

Transferable device-containing layer for silicon-on-insulator applications

Closed air gap interconnect structure

Copper recess process with application to selective capping and electroless plating

Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors

Field effect transistor with electroplated metal gate

Isolated sidewall capacitor having a compound plate electrode

Low temperature formation of low resistivity titanium silicide

Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics

Multilayer interconnect structure containing air gaps and method for making

Field effect transistor with etched-back gate dielectric

Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence

Isolated sidewall capacitor with dual dielectric

Orientation-optimized PFETS in CMOS devices employing dual stress liners

Method of forming closed air gap interconnects and structures formed thereby

Method of forming closed air gap interconnects and structures formed thereby

Diaphragm activated micro-electromechanical switch

Copper recess process with application to selective capping and electroless plating

Metal carbide gate structure and method of fabrication

Transferable device-containing layer for silicon-on-insulator applications

Field effect transistor with electroplated metal gate

Crack-tolerant photovoltaic cell structure and fabrication method

Method of forming a flexible semiconductor layer and devices on a flexible carrier

Methods to reduce debonding forces on flexible semiconductor films disposed on vapor-releasing adhesives

Carbon nanostructure device fabrication utilizing protect layers

CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins

Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow

Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers

Metal carbide gate structure and method of fabrication

Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates

Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow

Dual SIMOX hybrid orientation technology (HOT) substrates

Micro-electromechanical switch having a conductive compressible electrode

Amorphization/templated recrystallization method for hybrid orientation substrates

Amorphization/templated recrystallization method for hybrid orientation substrates

Carbon nanostructure device fabrication utilizing protect layers

Method of forming a flexible semiconductor layer and devices on a flexible carrier

Methods to reduce debonding forces on flexible semiconductor films disposed on vapor-releasing adhesives

Low temperature formation of low resistivity titanium silicide

COHEN GUY M

CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins

CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins

DE SOUZA JOEL P

Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide

Strain preserving ion implantation methods

BEDELL STEPHEN W

Strained devices, methods of manufacture and design structures

CHEN ZHIHONG

Graphene or carbon nanotube devices with localized bottom gates and gate dielectric

PENG HONGBO

Precisely tuning feature sizes on hard masks via plasma treatment

BOL AGEETH A

Graphene formation utilizing solid phase carbon sources

TYBERG CHRISTY S

BEOL compatible FET structrure