Inventor

YIN HAIZHOU

US174 patents

⚠️ This page may combine multiple inventors who share the name “YIN HAIZHOU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YIN HAIZHOU

ZHU HUILONG

Semiconductor device and method for manufacturing the same

Method for manufacturing graphene nano-ribbon, mosfet and method for manufacturing the same

Method for fabricating contact electrode and semiconductor device

Method for making FINFETs and semiconductor structures formed therefrom

Semiconductor device and method for manufacturing the same

FinFET and method for manufacturing the same

Structure and method having asymmetrical junction or reverse halo profile for semiconductor on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET)

Structure and method having asymmetrical junction or reverse halo profile for semiconductor on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET)

Semiconductor device having fins of different heights and method for manufacturing the same

Non-volatile memory device using finfet and method for manufacturing the same

Flash memory device and method for manufacturing the same

Semiconductor substrate for manufacturing transistors having back-gates thereon

Semiconductor structure and method for manufacturing the same

Method for removing metallic nanotube

Method for forming semiconductor structure

MOSFET structure and method of fabricating the same using replacement channel layer

Method for manufacturing a high-performance semiconductor structure with a replacement gate process and a stress memorization technique

IBM

finFETS and methods of making same

Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics

Dual stress memorization technique for CMOS application

Orientation-optimized PFETS in CMOS devices employing dual stress liners

Device having self-aligned double gate formed by backside engineering, and device having super-steep retrograded island

Dual stress memorization technique for CMOS application

Buried stress isolation for high-performance CMOS technology

Strained MOS devices using source/drain epitaxy

Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates

Buried stress isolation for high-performance CMOS technology

Asymmetric epitaxy and application thereof

Amorphization/templated recrystallization method for hybrid orientation substrates

Embedded insulating band for controlling short-channel effect and leakage reduction for DSB process

Amorphization/templated recrystallization method for hybrid orientation substrates

YIN HAIZHOU

Transistor with primary and semiconductor spacer, method for manufacturing transistor, and semiconductor chip comprising the transistor

Gate stack structure, semiconductor device and method for manufacturing the same

Hybrid channel semiconductor device and method for forming the same

Semiconductor structure and method for manufacturing the same

Semiconductor structure and method for manufacturing the same

Method for forming a semiconductor device with stressed trench isolation

Asymmetric epitaxy and application thereof

Structure of high-K metal gate semiconductor transistor

Semiconductor structure and method for manufacturing the same

LUO ZHIJIONG

Fin transistor structure and method of fabricating the same

Fin transistor structure and method of fabricating the same

Inducing stress in CMOS device

Isolation structure, method for manufacturing the same, and semiconductor device having the structure

INST OF MICROELECTRONICS CAS

Semiconductor structure and method for manufacturing the same

Semiconductor devices and methods for manufacturing the same

Method for manufacturing MOSFET

Semiconductor structure and method of manufacturing the same

CHAN KEVIN K

finFETs and methods of making same

ZHONG HUICAI

Semiconductor device structure and method for manufacturing the same