Inventor
JACKSON BRYAN L
US33 patents
⚠️ This page may combine multiple inventors who share the name “JACKSON BRYAN L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
31 patentsUS9992057B2Jun 5, 2018
Yield tolerance in a neurosynaptic system
IBM12 citations84
US9924490B2Mar 20, 2018
Scaling multi-core neurosynaptic networks across chip boundaries
IBM7 citations84
US9852006B2Dec 26, 2017
Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits
IBM15 citations84
US9747545B2Aug 29, 2017
Self-timed, event-driven neurosynaptic core controller
IBM9 citations84
US9588937B2Mar 7, 2017
Array of processor core circuits with reversible tiers
IBM7 citations84
US9244124B2Jan 26, 2016
Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputs
IBM12 citations84
US9984324B2May 29, 2018
Dual deterministic and stochastic neurosynaptic core circuit
IBM6 citations83
US9558443B2Jan 31, 2017
Dual deterministic and stochastic neurosynaptic core circuit
IBM6 citations83
US10785745B2Sep 22, 2020
Scaling multi-core neurosynaptic networks across chip boundaries
IBM2 citations73
US10650301B2May 12, 2020
Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation
IBM2 citations73
US10454759B2Oct 22, 2019
Yield tolerance in a neurosynaptic system
IBM3 citations73
US10410109B2Sep 10, 2019
Peripheral device interconnections for neurosynaptic systems
IBM5 citations73
US10102474B2Oct 16, 2018
Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network
IBM3 citations73
US9940302B2Apr 10, 2018
Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array
IBM4 citations73
US9886662B2Feb 6, 2018
Converting spike event data to digital numeric data
IBM4 citations73
US9881252B2Jan 30, 2018
Converting digital numeric data to spike event data
IBM2 citations73
US11184221B2Nov 23, 2021
Yield tolerance in a neurosynaptic system
IBM0 citations63
US11049001B2Jun 29, 2021
Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network
IBM0 citations63
US10984307B2Apr 20, 2021
Peripheral device interconnections for neurosynaptic systems
IBM0 citations62
US10929747B2Feb 23, 2021
Dual deterministic and stochastic neurosynaptic core circuit
IBM0 citations62
US10769519B2Sep 8, 2020
Converting digital numeric data to spike event data
IBM1 citations62
US10832151B2Nov 10, 2020
Implementing stochastic networks using magnetic tunnel junctions
IBM0 citations52
US10755165B2Aug 25, 2020
Converting spike event data to digital numeric data
IBM0 citations52
US9797946B2Oct 24, 2017
Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputs
IBM0 citations52
US9792251B2Oct 17, 2017
Array of processor core circuits with reversible tiers
IBM0 citations52
US9368489B1Jun 14, 2016
Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array
IBM0 citations52
US10990872B2Apr 27, 2021
Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency
IBM0 citations51
US10740282B2Aug 11, 2020
Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array
IBM0 citations50
US10678741B2Jun 9, 2020
Coupling parallel event-driven computation with serial computation
IBM0 citations50
US9390368B2Jul 12, 2016
Coupling parallel event-driven computation with serial computation
IBM1 citations50
US11144553B2Oct 12, 2021
Streaming programmable point mapper and compute hardware
IBM0 citations49