Inventor
KANG INKUK
US22 patents
⚠️ This page may combine multiple inventors who share the name “KANG INKUK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CYPRESS SEMICONDUCTOR CORP
6 patentsUS9853039B1Dec 26, 2017
Split-gate flash cell formed on recessed substrate
CYPRESS SEMICONDUCTOR CORP16 citations92
US12029041B2Jul 2, 2024
Method of forming high-voltage transistor with thin gate poly
CYPRESS SEMICONDUCTOR CORP1 citations73
US10872898B2Dec 22, 2020
Embedded non-volatile memory device and fabrication method of the same
CYPRESS SEMICONDUCTOR CORP4 citations73
US10242996B2Mar 26, 2019
Method of forming high-voltage transistor with thin gate poly
CYPRESS SEMICONDUCTOR CORP1 citations73
US11690227B2Jun 27, 2023
Method of forming high-voltage transistor with thin gate poly
CYPRESS SEMICONDUCTOR CORP0 citations62
US10497710B2Dec 3, 2019
Split-gate flash cell formed on recessed substrate
CYPRESS SEMICONDUCTOR CORP0 citations52
ADVANCED MICRO DEVICES INC
4 patentsUS6963108B1Nov 8, 2005
Recessed channel
ADVANCED MICRO DEVICES INC37 citations92
US7060564B1Jun 13, 2006
Memory device and method of simultaneous fabrication of core and periphery of same
ADVANCED MICRO DEVICES INC12 citations82
US7288487B1Oct 30, 2007
Metal/oxide etch after polish to prevent bridging between adjacent features of a semiconductor structure
ADVANCED MICRO DEVICES INC9 citations74
US8026169B2Sep 27, 2011
Cu annealing for improved data retention in flash memory devices
ADVANCED MICRO DEVICES INC2 citations60
SPANSION LLC
4 patentsUS6974989B1Dec 13, 2005
Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing
SPANSION LLC13 citations83
US7242102B2Jul 10, 2007
Bond pad structure for copper metallization having increased reliability and method for fabricating same
SPANSION LLC6 citations62
US8742496B2Jun 3, 2014
Sonos memory cells having non-uniform tunnel oxide and methods for fabricating same
SPANSION LLC0 citations52
US7122465B1Oct 17, 2006
Method for achieving increased control over interconnect line thickness across a wafer and between wafers
SPANSION LLC1 citations51
FANG SHENQING
4 patentsUS8551858B2Oct 8, 2013
Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory
FANG SHENQING2 citations60
US8637918B2Jan 28, 2014
Method and device employing polysilicon scaling
FANG SHENQING0 citations51
US8487373B2Jul 16, 2013
SONOS memory cells having non-uniform tunnel oxide and methods for fabricating same
FANG SHENQING1 citations51
US8076199B2Dec 13, 2011
Method and device employing polysilicon scaling
FANG SHENQING1 citations51
FASL LLC
3 patentsUS7033957B1Apr 25, 2006
ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices
FASL LLC62 citations96
US6803275B1Oct 12, 2004
ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices
FASL LLC46 citations96
US6969886B1Nov 29, 2005
ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices
FASL LLC28 citations92