Inventor
BECKER WIREN D
US33 patents
⚠️ This page may combine multiple inventors who share the name “BECKER WIREN D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
31 patentsUS7113401B2Sep 26, 2006
System for airflow management in electronic enclosures
IBM40 citations92
US9625220B1Apr 18, 2017
Structurally dynamic heat sink
IBM19 citations91
US6323050B1Nov 27, 2001
Method for evaluating decoupling capacitor placement for VLSI chips
IBM26 citations91
US5477460ADec 19, 1995
Early high level net based analysis of simultaneous switching
IBM37 citations87
US9548551B1Jan 17, 2017
DIMM connector region vias and routing
IBM10 citations84
US8050174B2Nov 1, 2011
Self-healing chip-to-chip interface
IBM11 citations84
US6713686B2Mar 30, 2004
Apparatus and method for repairing electronic packages
IBM16 citations84
US10247489B2Apr 2, 2019
Structural dynamic heat sink
IBM7 citations82
US10135162B1Nov 20, 2018
Method for fabricating a hybrid land grid array connector
IBM8 citations82
US10128593B1Nov 13, 2018
Connector having a body with a conductive layer common to top and bottom surfaces of the body as well as to wall surfaces of a plurality of holes in the body
IBM6 citations82
US9644907B1May 9, 2017
Structurally dynamic heat sink
IBM8 citations82
US7465882B2Dec 16, 2008
Ceramic substrate grid structure for the creation of virtual coax arrangement
IBM10 citations82
US9444162B1Sep 13, 2016
DIMM connector region vias and routing
IBM4 citations73
US6529023B2Mar 4, 2003
Application and test methodology for use with compression land grid array connectors
IBM11 citations73
US11658378B2May 23, 2023
Vertically transitioning between substrate integrated waveguides (SIWs) within a multilayered printed circuit board (PCB)
IBM4 citations72
US6618844B2Sep 9, 2003
Method for evaluating decoupling capacitor placement for VLSI chips
IBM8 citations72
US6618843B2Sep 9, 2003
Method for evaluating decoupling capacitor placement for VLSI chips
IBM9 citations72
US9638750B2May 2, 2017
Frequency-domain high-speed bus signal integrity compliance model
IBM2 citations71
US6058488AMay 2, 2000
Method of reducing computer module cycle time
IBM12 citations70
US9627787B2Apr 18, 2017
DIMM connector region vias and routing
IBM1 citations63
US8018837B2Sep 13, 2011
Self-healing chip-to-chip interface
IBM2 citations63
US10257599B2Apr 9, 2019
Slack and strain control mechanism
IBM1 citations62
US7985927B2Jul 26, 2011
Ceramic substrate grid structure for the creation of virtual coax arrangement
IBM1 citations61
US7897879B2Mar 1, 2011
Ceramic substrate grid structure for the creation of virtual coax arrangement
IBM1 citations61
US7826579B2Nov 2, 2010
Method and apparatus for generating synchronization signals for synchronizing multiple chips in a system
IBM4 citations61
US11399428B2Jul 26, 2022
PCB with substrate integrated waveguides using multi-band monopole antenna feeds for high speed communication
IBM0 citations60
US7355125B2Apr 8, 2008
Printed circuit board and chip module
IBM4 citations60
US7742315B2Jun 22, 2010
Circuit on a printed circuit board
IBM1 citations51
US9733305B2Aug 15, 2017
Frequency-domain high-speed bus signal integrity compliance model
IBM0 citations50
US9686053B2Jun 20, 2017
Frequency-domain high-speed bus signal integrity compliance model
IBM0 citations50
US9673941B2Jun 6, 2017
Frequency-domain high-speed bus signal integrity compliance model
IBM0 citations50