Inventor
AMANAPU HARI PRASAD
US12 patents
Patents
12 patentsUS10978388B2Apr 13, 2021
Skip via for metal interconnects
IBM3 citations71
US10832946B1Nov 10, 2020
Recessed interconnet line having a low-oxygen cap for facilitating a robust planarization process and protecting the interconnect line from downstream etch operations
IBM3 citations69
US10818589B2Oct 27, 2020
Metal interconnect structures with self-forming sidewall barrier layer
IBM2 citations68
US11908923B2Feb 20, 2024
Low-resistance top contact on VTFET
IBM0 citations62
US11024720B2Jun 1, 2021
Non-self aligned contact semiconductor devices
IBM0 citations62
US10833173B2Nov 10, 2020
Low-resistance top contact on VTFET
IBM1 citations62
US11800817B2Oct 24, 2023
Phase change memory cell galvanic corrosion prevention
IBM0 citations60
US11037795B2Jun 15, 2021
Planarization of dielectric topography and stopping in dielectric
IBM0 citations60
US11127825B2Sep 21, 2021
Middle-of-line contacts with varying contact area providing reduced contact resistance
IBM0 citations51
US11637036B2Apr 25, 2023
Planarization stop region for use with low pattern density interconnects
IBM0 citations50
US10833122B2Nov 10, 2020
Bottom electrode and dielectric structure for MRAM applications
IBM0 citations50
US10916431B2Feb 9, 2021
Robust gate cap for protecting a gate from downstream metallization etch operations
IBM0 citations46