Inventor

HORCH ANDREW E

US42 patents

⚠️ This page may combine multiple inventors who share the name “HORCH ANDREW E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HORCH ANDREW E

SYNOPSYS INC

One-time programmable memory using rupturing of gate insulation

Non-volatile memory devices having floating-gates FETs with different source-gate and drain-gate border lengths

One-time programmable bitcell with partially native select device

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

RFID tag having non-volatile memory device having floating-gate FETs with different source-gate and drain-gate border lengths

Non-volatile memory cell with BTBT programming

One-time programmable bitcell with diode under anti-fuse

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

RFID tag having non-volatile memory device having floating-gate FETs with different source-gate and drain-gate border lengths

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

One-time programmable bitcell with native anti-fuse

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

Very dense nonvolatile memory bitcell

NVM device using FN tunneling with parallel powered source and drain

One-time programmable bitcell with native anti-fuse

T RAM SEMICONDUCTOR INC

Vertical thyristor-based memory with trench isolation and its method of fabrication

Thyristor circuit and approach for temperature stability

Vertical thyristor-based memory with trench isolation and method of fabrication thereof

Semiconductor device incorporating thyristor-based memory and strained silicon

Method of manufacturing a thyristor semiconductor device

Semiconductor device with leakage implant and method of fabrication

Thyristor semiconductor memory device and method of manufacture

Gated-thyristor approach having angle-implanted base region

Thyristor semiconductor memory device and method of manufacture

Thyristor semiconductor device and method of manufacture

HORCH ANDREW E

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

Non-volatile memory cell with BTBT programming

NVM bitcell with a replacement control gate and additional floating gate

Very dense NVM bitcell

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

IMPINJ INC

Wireless functional testing of RFID tag

Etch before grind for semiconductor die singulation

On die RFID tag antenna

RFID tag circuit die with shielding layer to control I/O bump flow

VIRAGE LOGIC CORP

Non-volatile memory cell circuit with programming through band-to-band tunneling and impact ionization gate current

Non-volatile memory with programming through band-to-band tunneling and impact ionization gate current

Non-volatile memory cell circuit with programming through band-to-band tunneling and impact ionization gate current

Multi-level non-volatile memory cell with high-VT enhanced BTBT device

T RAM INC

Thyrister semiconductor device

LINDHORST CHAD A

One time programmable memory test structures and methods