Inventor

COON BRETT W

US58 patents

⚠️ This page may combine multiple inventors who share the name “COON BRETT W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

COON BRETT W

NVIDIA CORP

Synchronization of threads in a cooperative thread array

Maximized memory throughput using cooperative thread arrays

Structured programming control flow in a SIMD architecture

Single interconnect providing read and write access to a memory shared by concurrent threads

System and method for managing divergent threads in a SIMD architecture

Structured programming control flow using a disable mask in a SIMD architecture

System and method for managing divergent threads using synchronization tokens and program instructions that include set-synchronization bits

Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicators

Scheduling instructions from multi-thread instruction buffer based on phase boundary qualifying rule for phases of math and data access operations with better caching

Processing an indirect branch instruction in a SIMD architecture

Apparatus and method for monitoring and debugging a graphics processing unit

Lock mechanism to enable atomic updates to shared memory

Scheduler in multi-threaded processor prioritizing instructions passing qualification rule

Operand collector architecture

Apparatus and method for debugging a graphics processing unit in response to a debug instruction

Register file allocation

Subdividing a shader program

Register based queuing for texture requests

Prioritized issuing of operation dedicated execution unit tagged instructions from multiple different type threads performing different set of operations

Instructions for managing a parallel cache hierarchy

Indirect function call instructions in a synchronous parallel thread processor

Lock mechanism to enable atomic updates to shared memory

System and method for processing thread groups in a SIMD architecture

Generating event signals for performance register control using non-operative instructions

Multi-threaded stack cache

Programmable graphics processor for multithreaded execution of programs

Register based queuing for texture requests

Cooperative thread array reduction and scan operations

Programmable graphics processor for multithreaded execution of programs

Cooperative thread array reduction and scan operations

COON BRETT W

Shared memory with parallel access and access conflict resolution mechanism

Scoreboard having size indicators for tracking sequential destination register usage in a multi-threaded processor

Soldier-on mode to control processor error handling behavior

Thread group scheduler for computing on a parallel thread processor

Indirect function call instructions in a synchronous parallel thread processor

Shared single-access memory with management of multiple parallel requests

Systems and method for managing divergent threads in a SIMD architecture

LINDHOLM JOHN ERIK

Programmable graphics processor for multithreaded execution of programs

Programmable graphics processor for multithreaded execution of programs

Subdividing a shader program

Credit-based streaming multiprocessor warp scheduling

NICKOLLS JOHN R

Coalescing memory barrier operations across multiple parallel threads

Unified addressing and instructions for accessing parallel memory spaces

FAHS BRIAN

Efficient implementation of arrays of structures on SIMT and SIMD architectures

Cooperative thread array reduction and scan operations

NORDQUIST BRYON S

Managing state information for a multi-threaded processor

JUFFA NORBERT

Maximized memory throughput on parallel processing devices

HEINRICH STEVEN JAMES

Cache operations and policies for a multi-threaded client

SHEBANOW MICHAEL C

Trap handler architecture for a parallel processing unit

MINKIN ALEXANDER L

Configurable cache for multiple clients