Inventor
QI JIEMING
US76 patents
⚠️ This page may combine multiple inventors who share the name “QI JIEMING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
41 patentsUS7322001B2Jan 22, 2008
Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance
IBM18 citations93
US7245161B2Jul 17, 2007
Apparatus and method for verifying glitch-free operation of a multiplexer
IBM22 citations93
US7200064B1Apr 3, 2007
Apparatus and method for providing a reprogrammable electrically programmable fuse
IBM20 citations93
US6404235B1Jun 11, 2002
System and method for reducing latency in a dynamic circuit
IBM23 citations93
US7913199B2Mar 22, 2011
Structure for a duty cycle correction circuit
IBM8 citations84
US7877222B2Jan 25, 2011
Structure for a phase locked loop with adjustable voltage based on temperature
IBM7 citations84
US7675338B2Mar 9, 2010
Duty cycle correction circuit whose operation is largely independent of operating voltage and process
IBM15 citations84
US7595675B2Sep 29, 2009
Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode
IBM8 citations84
US7493229B2Feb 17, 2009
Adjusting voltage for a phase locked loop based on temperature
IBM8 citations84
US7417480B2Aug 26, 2008
Duty cycle correction circuit whose operation is largely independent of operating voltage and process
IBM9 citations84
US7363178B2Apr 22, 2008
Method and apparatus for measuring the relative duty cycle of a clock signal
IBM10 citations84
US7360135B2Apr 15, 2008
Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance
IBM14 citations84
US7356716B2Apr 8, 2008
System and method for automatic calibration of a reference voltage
IBM9 citations84
US7350095B2Mar 25, 2008
Digital circuit to measure and/or correct duty cycles
IBM9 citations84
US7330061B2Feb 12, 2008
Method and apparatus for correcting the duty cycle of a digital signal
IBM12 citations84
US7245172B2Jul 17, 2007
Level shifter apparatus and method for minimizing duty cycle distortion
IBM13 citations84
US7113881B2Sep 26, 2006
Method and apparatus for semi-automatic extraction and monitoring of diode ideality in a manufacturing environment
IBM14 citations84
US6819141B1Nov 16, 2004
High speed, static digital multiplexer
IBM13 citations84
US7420400B2Sep 2, 2008
Method and apparatus for on-chip duty cycle measurement
IBM7 citations74
US7333905B2Feb 19, 2008
Method and apparatus for measuring the duty cycle of a digital signal
IBM8 citations74
US7132896B2Nov 7, 2006
Circuit for minimizing filter capacitance leakage induced jitter in phase locked loops (PPLs)
IBM8 citations74
US9444657B2Sep 13, 2016
Dynamically calibrating the offset of a receiver with a decision feedback equalizer (DFE) while performing data transport operations
IBM3 citations73
US8037431B2Oct 11, 2011
Structure for interleaved voltage controlled oscillator
IBM5 citations72
US7391277B2Jun 24, 2008
Interleaved voltage controlled oscillator
IBM8 citations72
US11804828B2Oct 31, 2023
Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter output
IBM3 citations71
US8032850B2Oct 4, 2011
Structure for an absolute duty cycle measurement circuit
IBM3 citations63
US7969250B2Jun 28, 2011
Structure for a programmable interpolative voltage controlled oscillator with adjustable range
IBM6 citations63
US7917795B2Mar 29, 2011
Digital circuit to measure and/or correct duty cycles
IBM2 citations63
US7917318B2Mar 29, 2011
Structure for a duty cycle measurement circuit
IBM4 citations63
US7904264B2Mar 8, 2011
Absolute duty cycle measurement
IBM4 citations63
US7747892B2Jun 29, 2010
System for automatically selecting intermediate power supply voltages for intermediate level shifters
IBM3 citations63
US7701269B2Apr 20, 2010
Method and system for managing voltage swings across field effect transistors
IBM2 citations63
US7646177B2Jan 12, 2010
Design structure for a duty cycle measurement apparatus that operates in a calibration mode and a test mode
IBM5 citations63
US7617059B2Nov 10, 2009
Method and apparatus for measuring the duty cycle of a digital signal
IBM5 citations63
US7589575B2Sep 15, 2009
Precision integrated phase lock loop circuit loop filter
IBM4 citations63
US7358785B2Apr 15, 2008
Apparatus and method for extracting a maximum pulse width of a pulse width limiter
IBM5 citations63
US7321651B2Jan 22, 2008
High frequency circuit capable of error detection and correction of code patterns running at full speed
IBM4 citations63
US7265600B2Sep 4, 2007
Level shifter system and method to minimize duty cycle error due to voltage differences across power domains
IBM2 citations63
US7260491B2Aug 21, 2007
Duty cycle measurement apparatus and method
IBM6 citations63
US12095891B2Sep 17, 2024
Communication systems for power supply noise reduction
IBM0 citations62
US11979480B2May 7, 2024
Quadrature circuit interconnect architecture with clock forwarding
IBM0 citations62
EVERSPIN TECHNOLOGIES INC
3 patentsUS10056909B1Aug 21, 2018
Single-lock delay locked loop with cycle counter and method therefore
EVERSPIN TECHNOLOGIES INC19 citations93
US10250265B2Apr 2, 2019
Single-lock delay locked loop with cycle counter and method therefor
EVERSPIN TECHNOLOGIES INC2 citations73
US10608648B2Mar 31, 2020
Single-lock delay locked loop with cycle counter and method therefor
EVERSPIN TECHNOLOGIES INC1 citations72
TOSHIBA KK
3 patentsUS7511554B2Mar 31, 2009
Systems and methods for level shifting using AC coupling
TOSHIBA KK20 citations93
US7642863B2Jan 5, 2010
Systems and methods for PLL linearity measurement, PLL output duty cycle measurement and duty cycle correction
TOSHIBA KK5 citations63
US7030658B2Apr 18, 2006
Systems and methods for operating logic circuits
TOSHIBA KK2 citations63
ANALOG DEVICES INC
1 patentBOERSTLER DAVID WILLIAM
1 patentSONY COMPUTER ENTERTAINMENT INC
1 patentShowing the top 50 of 76 patents by PatentIndex Score.