Inventor

DHONG SANG HOO

US124 patents

⚠️ This page may combine multiple inventors who share the name “DHONG SANG HOO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DHONG SANG HOO

IBM

Method for integrated circuit power and electrical connections via through-wafer interconnects

Communications bus with redundant signal paths and method for compensating for signal path errors in a communications bus

Silicon packaging with through wafer interconnects

Multiprocessor with pair-wise high reliability mode, and method therefore

Symmetric multiprocessor coherence mechanism

At-speed scan testing

Method for performing address mapping using two lookup tables

32-bit and 64-bit dual mode rotator

Fast low-power logic gates and method for evaluating logic signals

High-speed binary adder

Multiple level cache memory with overlapped L1 and L2 memory access

Set associative cache memory system with reduced power consumption

Method for reducing power consumption in a set associative cache memory system

High-speed binary adder

Ring-topology based multiprocessor data access bus

Set-associative cache memory having a built-in set prediction array

Destructive read architecture for dynamic random access memories

Cycle control circuit for extending a cycle period of a dynamic memory device subarray

Level shifter for boosting wordline voltage and memory cell performance

Power saving in a floating point unit using a multiplier and aligner bypass

Method and apparatus for creating improved inductors for use with electronic oscillators

High performance registers for pulsed logic

Power saving in FPU with gated power based on opcodes and data

Unified local clock buffer structures

Latching dynamic logic structure, and integrated circuit including same

Method and system for accessing a cache memory within a data processing system

Method and apparatus for implementing logic using mask-programmable dynamic logic gates

Low latency fused multiply-adder

Impedane measurement of chip, package, and board power supply system using pseudo impulse response

Integrated logic and latch design with clock gating at static input signals

Method and apparatus for evaluating results of multiple software tools

4 to 2 adder

Processor cycle time independent pipeline cache and method for pipelining data from a cache

High performance implementation of exponent adjustment in a floating point design

Leading-zero anticipator having an independent sign bit determination module

Processor and method for generating less than (LT), Greater than (GT), and equal to (EQ) condition code bits concurrent with a logical or complex operation

Memory design which facilitates incremental fetch and store requests off applied base address requests

Memory with combined line and word access

Protecting one-hot logic against short-circuits during power-on

Scannable latch

Scan chain disable function for power saving

Low skew, power efficient local clock signal generation system

Apparatus and method of wordline/bitline redundancy control using shift registers in an SRAM

Method and apparatus for cycle time reduction in a memory system using alternating reference cells and isolated sense lines

6-to-3 carry-save adder

DHONG SANG HOO

Planar compatible FDSOI design architecture

Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units

TAIWAN SEMICONDUCTOR MFG

Electron beam lithography methods including time division multiplex loading

Electron beam lithography systems and methods including time division multiplex loading

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor structure