Inventor
WILLIAMS THOMAS W
US29 patents
⚠️ This page may combine multiple inventors who share the name “WILLIAMS THOMAS W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SYNOPSYS INC
19 patentsUS6950974B1Sep 27, 2005
Efficient compression and application of deterministic patterns in a logic BIST architecture
SYNOPSYS INC92 citations98
US6615380B1Sep 2, 2003
Dynamic scan chains and test pattern generation methodologies therefor
SYNOPSYS INC91 citations98
US6385750B1May 7, 2002
Method and system for controlling test data volume in deterministic test pattern generation
SYNOPSYS INC97 citations97
US6993694B1Jan 31, 2006
Deterministic bist architecture including MISR filter
SYNOPSYS INC75 citations96
US6807646B1Oct 19, 2004
System and method for time slicing deterministic patterns for reseeding in logic built-in self-test
SYNOPSYS INC61 citations96
US7418640B2Aug 26, 2008
Dynamically reconfigurable shared scan-in test architecture
SYNOPSYS INC28 citations94
US7900105B2Mar 1, 2011
Dynamically reconfigurable shared scan-in test architecture
SYNOPSYS INC15 citations92
US6766501B1Jul 20, 2004
System and method for high-level test planning for layout
SYNOPSYS INC34 citations92
US6631344B1Oct 7, 2003
Method and system for performing deterministic analysis and speculative analysis for more efficient automatic test pattern generation
SYNOPSYS INC41 citations92
US6453437B1Sep 17, 2002
Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation
SYNOPSYS INC32 citations92
US6434733B1Aug 13, 2002
System and method for high-level test planning for layout
SYNOPSYS INC39 citations92
US6405355B1Jun 11, 2002
Method for placement-based scan-in and scan-out ports selection
SYNOPSYS INC43 citations92
US7669098B2Feb 23, 2010
Method and apparatus for limiting power dissipation in test
SYNOPSYS INC8 citations84
US7774663B2Aug 10, 2010
Dynamically reconfigurable shared scan-in test architecture
SYNOPSYS INC8 citations83
US7596733B2Sep 29, 2009
Dynamically reconfigurable shared scan-in test architecture
SYNOPSYS INC8 citations83
US7814444B2Oct 12, 2010
Scan compression circuit and method of design therefor
SYNOPSYS INC16 citations81
US7836367B2Nov 16, 2010
Dynamically reconfigurable shared scan-in test architecture
SYNOPSYS INC7 citations73
US7836368B2Nov 16, 2010
Dynamically reconfigurable shared scan-in test architecture
SYNOPSYS INC3 citations73
US7743299B2Jun 22, 2010
Dynamically reconfigurable shared scan-in test architecture
SYNOPSYS INC2 citations62
IBM
5 patentsUS4503386AMar 5, 1985
Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks
IBM80 citations95
US4293919AOct 6, 1981
Level sensitive scan design (LSSD) system
IBM61 citations94
US4509008AApr 2, 1985
Method of concurrently testing each of a plurality of interconnected integrated circuit chips
IBM56 citations91
US4277699AJul 7, 1981
Latch circuit operable as a D-type edge trigger
IBM24 citations78
US4726023AFeb 16, 1988
Determination of testability of combined logic end memory by ignoring memory
IBM8 citations74