Inventor
GUO JYH-CHYURN
TW21 patents
⚠️ This page may combine multiple inventors who share the name “GUO JYH-CHYURN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
12 patentsUS6596599B1Jul 22, 2003
Gate stack for high performance sub-micron CMOS devices
TAIWAN SEMICONDUCTOR MFG294 citations99
US6894357B2May 17, 2005
Gate stack for high performance sub-micron CMOS devices
TAIWAN SEMICONDUCTOR MFG39 citations92
US6596594B1Jul 22, 2003
Method for fabricating field effect transistor (FET) device with asymmetric channel region and asymmetric source and drain regions
TAIWAN SEMICONDUCTOR MFG38 citations92
US6528376B1Mar 4, 2003
Sacrificial spacer layer method for fabricating field effect transistor (FET) device
TAIWAN SEMICONDUCTOR MFG45 citations92
US6888063B1May 3, 2005
Device and method for providing shielding in radio frequency integrated circuits to reduce noise coupling
TAIWAN SEMICONDUCTOR MFG42 citations91
US6847098B1Jan 25, 2005
Non-floating body device with enhanced performance
TAIWAN SEMICONDUCTOR MFG18 citations91
US6878964B1Apr 12, 2005
Ground-signal-ground pad layout for device tester structure
TAIWAN SEMICONDUCTOR MFG18 citations84
US6835622B2Dec 28, 2004
Gate electrode doping method for forming semiconductor integrated circuit microelectronic fabrication with varying effective gate dielectric layer thicknesses
TAIWAN SEMICONDUCTOR MFG15 citations84
US6627515B1Sep 30, 2003
Method of fabricating a non-floating body device with enhanced performance
TAIWAN SEMICONDUCTOR MFG8 citations72
US6878583B2Apr 12, 2005
Integration method to enhance p+ gate activation
TAIWAN SEMICONDUCTOR MFG6 citations63
US7071478B2Jul 4, 2006
System and method for passing particles on selected areas on a wafer
TAIWAN SEMICONDUCTOR MFG4 citations61
US6660635B1Dec 9, 2003
Pre-LDD wet clean recipe to gain channel length scaling margin beyond sub-0.1 μm
TAIWAN SEMICONDUCTOR MFG0 citations42
MACRONIX INT CO LTD
3 patentsUS5918125AJun 29, 1999
Process for manufacturing a dual floating gate oxide flash memory cell
MACRONIX INT CO LTD45 citations91
US6009017ADec 28, 1999
Floating gate memory with substrate band-to-band tunneling induced hot electron injection
MACRONIX INT CO LTD33 citations88
US6352886B2Mar 5, 2002
Method of manufacturing floating gate memory with substrate band-to-band tunneling induced hot electron injection
MACRONIX INT CO LTD1 citations48
VANGUARD INT SEMICONDUCT CORP
3 patentsUS6529427B1Mar 4, 2003
Test structures for measuring DRAM cell node junction leakage current
VANGUARD INT SEMICONDUCT CORP13 citations84
US6323077B1Nov 27, 2001
Inverse source/drain process using disposable sidewall spacer
VANGUARD INT SEMICONDUCT CORP18 citations84
US6103580AAug 15, 2000
Method to form ultra-shallow buried-channel MOSFETs
VANGUARD INT SEMICONDUCT CORP17 citations84