Inventor

TONTI WILLIAM ROBERT

US54 patents

⚠️ This page may combine multiple inventors who share the name “TONTI WILLIAM ROBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TONTI WILLIAM ROBERT

IBM

Semiconductor structures integrating damascene-body FinFET&#39;s and planar devices on a common substrate and methods for forming such semiconductor structures

Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates

Impedance control using fuses

Managing Vt for reduced power using a status table

Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox

Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality

Chip thermal protection device

Switched body SOI (silicon on insulator) circuits and fabrication method therefor

Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality

Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures

Self-aligned, planarized thin-film transistors, devices employing the same

Semiconductor structures integrating damascene-body FinFET&#39;s and planar devices on a common substrate and methods for forming such semiconductor structures

Semiconductor structures integrating damascene-body FinFET&#39;s and planar devices on a common substrate and methods for forming such semiconductor structures

Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors

Impedance control using fuses

Intrinsic dual gate oxide MOSFET using a damascene gate process

Electronic fuses in semiconductor integrated circuits

Interconnect structures with improved electromigration resistance and methods for forming such interconnect structures

Methods and semiconductor structures for latch-up suppression using a conductive region

Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures

Methods and semiconductor structures for latch-up suppression using a conductive region

Methods of implementing and enhanced silicon-on-insulator (SOI) box structures

Intrinsic dual gate oxide MOSFET using a damascene gate process

Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures

Methods and semiconductor structures for latch-up suppression using a conductive region

Design structures incorporating interconnect structures with liner repair layers

Interconnect structures with linear repair layers and methods for forming such interconnection structures

Self-aligned, planarized thin-film transistors, devices employing the same, and methods of fabrication thereof

Providing dual work function doping

Device for monitoring ionizing radiation in silicon-on insulator integrated circuits

Monitoring ionizing radiation in silicon-on insulator integrated circuits

Semiconductor transistors with contact holes close to gates

Structures incorporating interconnect structures with improved electromigration resistance

Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes

Thin gate electrode CMOS devices and methods of fabricating same

Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates

Latch-up resistant semiconductor structures on hybrid substrates and methods for forming such semiconductor structures

Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices

Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates

Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates

Well isolation trenches (WIT) for CMOS devices

Hybrid substrates and methods for forming such hybrid substrates

Method of fabricating semiconductor structures for latch-up suppression

Resettable fuse device and method of fabricating the same

High-voltage silicon-on-insulator transistors and methods of manufacturing the same

Well isolation trenches (WIT) for CMOS devices

Crystal imprinting methods for fabricating substrates with thin active silicon layers

INFINEON TECHNOLOGIES AG

Wordline on and off voltage compensation circuit based on the array device threshold voltage

TONTI WILLIAM ROBERT

Method and system for selective stress enablement in simulation modeling

CHATTY KIRAN V

Enhanced stress-retention fin-FET devices and methods of fabricating enhanced stress retention fin-FET devices

Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures

Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures

Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures