P

Inventor

JANG KIYOUN

KR29 patents
⚠️ This page may combine multiple inventors who share the name “JANG KIYOUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STATS CHIPPAC LTD

11 patents
US9117812B2Aug 25, 2015

Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability

STATS CHIPPAC LTD7 citations84
US8519536B2Aug 27, 2013

Semiconductor device including bump formed on substrate to prevent extremely-low dielectric constant (ELK) interlayer dielectric layer (ILD) delamination during reflow process

STATS CHIPPAC LTD5 citations84
US8367467B2Feb 5, 2013

Semiconductor method of forming bump on substrate to prevent ELK ILD delamination during reflow process

STATS CHIPPAC LTD5 citations84
US8039384B2Oct 18, 2011

Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces

STATS CHIPPAC LTD13 citations84
US9030030B2May 12, 2015

Semiconductor device and method of forming adjacent channel and dam material around die attach area of substrate to control outward flow of underfill material

STATS CHIPPAC LTD8 citations83
US9236332B2Jan 12, 2016

Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe

STATS CHIPPAC LTD4 citations73
US8884339B2Nov 11, 2014

Semiconductor device with bump formed on substrate to prevent ELK ILD delamination during reflow process

STATS CHIPPAC LTD1 citations62
US7897502B2Mar 1, 2011

Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers

STATS CHIPPAC LTD1 citations62
US8896133B2Nov 25, 2014

Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate

STATS CHIPPAC LTD1 citations52
US8742566B2Jun 3, 2014

Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingers

STATS CHIPPAC LTD0 citations52
US9460972B2Oct 4, 2016

Semiconductor device and method of forming reduced surface roughness in molded underfill for improved C-SAM inspection

STATS CHIPPAC LTD1 citations50

SAMSUNG ELECTRONICS CO LTD

8 patents

LEE JAEHYUN

3 patents

LEE KYUNGHOON

2 patents

PAGAILA REZA A

2 patents

JANG KIYOUN

2 patents

CHO SUNGWON

1 patent