Inventor
JANG KIYOUN
KR29 patents
⚠️ This page may combine multiple inventors who share the name “JANG KIYOUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
STATS CHIPPAC LTD
11 patentsUS9117812B2Aug 25, 2015
Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability
STATS CHIPPAC LTD7 citations84
US8519536B2Aug 27, 2013
Semiconductor device including bump formed on substrate to prevent extremely-low dielectric constant (ELK) interlayer dielectric layer (ILD) delamination during reflow process
STATS CHIPPAC LTD5 citations84
US8367467B2Feb 5, 2013
Semiconductor method of forming bump on substrate to prevent ELK ILD delamination during reflow process
STATS CHIPPAC LTD5 citations84
US8039384B2Oct 18, 2011
Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces
STATS CHIPPAC LTD13 citations84
US9030030B2May 12, 2015
Semiconductor device and method of forming adjacent channel and dam material around die attach area of substrate to control outward flow of underfill material
STATS CHIPPAC LTD8 citations83
US9236332B2Jan 12, 2016
Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe
STATS CHIPPAC LTD4 citations73
US8884339B2Nov 11, 2014
Semiconductor device with bump formed on substrate to prevent ELK ILD delamination during reflow process
STATS CHIPPAC LTD1 citations62
US7897502B2Mar 1, 2011
Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers
STATS CHIPPAC LTD1 citations62
US8896133B2Nov 25, 2014
Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
STATS CHIPPAC LTD1 citations52
US8742566B2Jun 3, 2014
Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingers
STATS CHIPPAC LTD0 citations52
US9460972B2Oct 4, 2016
Semiconductor device and method of forming reduced surface roughness in molded underfill for improved C-SAM inspection
STATS CHIPPAC LTD1 citations50
SAMSUNG ELECTRONICS CO LTD
8 patentsUS10158261B2Dec 18, 2018
Electronic device having wireless power transmitting/receiving conductive pattern
SAMSUNG ELECTRONICS CO LTD5 citations83
US10785887B2Sep 22, 2020
Electronic device including cooling function and controlling method thereof
SAMSUNG ELECTRONICS CO LTD6 citations82
US10680470B2Jun 9, 2020
Electronic device having wireless power transmitting/receiving conductive pattern
SAMSUNG ELECTRONICS CO LTD2 citations72
US11990786B2May 21, 2024
Electronic device and method for controlling cooling function of external electronic device
SAMSUNG ELECTRONICS CO LTD0 citations61
US12287684B2Apr 29, 2025
Electronic device including heat transfer member
SAMSUNG ELECTRONICS CO LTD1 citations56
US11695291B2Jul 4, 2023
Method to charge battery and electronic device including battery
SAMSUNG ELECTRONICS CO LTD1 citations52
US12334578B2Jun 17, 2025
Electronic device including battery
SAMSUNG ELECTRONICS CO LTD0 citations48
US12548866B2Feb 10, 2026
Pouch-type flexible battery
SAMSUNG ELECTRONICS CO LTD0 citations45
LEE JAEHYUN
3 patentsUS8642384B2Feb 4, 2014
Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability
LEE JAEHYUN6 citations83
US9054100B2Jun 9, 2015
Semiconductor die and method of forming sloped surface in photoresist layer to enhance flow of underfill material between semiconductor die and substrate
LEE JAEHYUN3 citations62
US9230933B2Jan 5, 2016
Semiconductor device and method of forming conductive protrusion over conductive pillars or bond pads as fixed offset vertical interconnect structure
LEE JAEHYUN2 citations60
LEE KYUNGHOON
2 patentsUS8399300B2Mar 19, 2013
Semiconductor device and method of forming adjacent channel and DAM material around die attach area of substrate to control outward flow of underfill material
LEE KYUNGHOON38 citations93
US10096540B2Oct 9, 2018
Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for maintaining standoff distance
LEE KYUNGHOON1 citations50
PAGAILA REZA A
2 patentsUS8563418B2Oct 22, 2013
Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces
PAGAILA REZA A8 citations84
US8409978B2Apr 2, 2013
Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe
PAGAILA REZA A5 citations73
JANG KIYOUN
2 patentsUS8169071B2May 1, 2012
Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingers
JANG KIYOUN7 citations81
US8389398B2Mar 5, 2013
Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers
JANG KIYOUN0 citations49