Inventor
ROBINSON ERIC F
US26 patents
⚠️ This page may combine multiple inventors who share the name “ROBINSON ERIC F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
11 patentsUS7934081B2Apr 26, 2011
Apparatus and method for using branch prediction heuristics for determination of trace formation readiness
IBM8 citations83
US7644233B2Jan 5, 2010
Apparatus and method for supporting simultaneous storage of trace and standard cache lines
IBM8 citations83
US9645931B2May 9, 2017
Filtering snoop traffic in a multiprocessor computing system
IBM6 citations82
US5898843AApr 27, 1999
System and method for controlling device which is present in media console and system unit of a split computer system
IBM19 citations79
US8352646B2Jan 8, 2013
Direct access to cache memory
IBM6 citations69
US8386712B2Feb 26, 2013
Structure for supporting simultaneous storage of trace and standard cache lines
IBM4 citations62
US7996618B2Aug 9, 2011
Apparatus and method for using branch prediction heuristics for determination of trace formation readiness
IBM3 citations62
US7610449B2Oct 27, 2009
Apparatus and method for saving power in a trace cache
IBM2 citations62
US9323675B2Apr 26, 2016
Filtering snoop traffic in a multiprocessor computing system
IBM0 citations51
US7752393B2Jul 6, 2010
Design structure for forwarding store data to loads in a pipelined processor
IBM1 citations48
US7689870B2Mar 30, 2010
Efficient and flexible trace trigger handling for non-concurrent events
IBM0 citations36
COX JASON A
5 patentsUS8656106B2Feb 18, 2014
Managing unforced injections of cache lines into a cache utilizing predetermined address ranges
COX JASON A10 citations81
US8707449B2Apr 22, 2014
Acquiring access to a token controlled system resource
COX JASON A2 citations59
US8639889B2Jan 28, 2014
Address-based hazard resolution for managing read/write operations in a memory cache
COX JASON A3 citations58
US8671247B2Mar 11, 2014
Transfer of bus-based operations to demand-side machines
COX JASON A1 citations48
US8938588B2Jan 20, 2015
Ensuring forward progress of token-required cache operations in a shared cache
COX JASON A0 citations40
ADAR ETAI
4 patentsUS8589922B2Nov 19, 2013
Performance monitor design for counting events generated by thread groups
ADAR ETAI7 citations82
US8489787B2Jul 16, 2013
Sharing sampled instruction address registers for efficient instruction sampling in massively multithreaded processors
ADAR ETAI14 citations82
US8601193B2Dec 3, 2013
Performance monitor design for instruction profiling using shared counters
ADAR ETAI2 citations61
US8417851B2Apr 9, 2013
Polling of a target register within a peripheral device
ADAR ETAI0 citations39
ROBINSON ERIC F
4 patentsUS8112604B2Feb 7, 2012
Tracking load store ordering hazards
ROBINSON ERIC F4 citations60
US9170962B2Oct 27, 2015
Dynamic designation of retirement order in out-of-order store queue
ROBINSON ERIC F0 citations50
US8930680B2Jan 6, 2015
Sync-ID for multiple concurrent sync dependencies in an out-of-order store queue
ROBINSON ERIC F1 citations50
US8131953B2Mar 6, 2012
Tracking store ordering hazards in an out-of-order store queue
ROBINSON ERIC F1 citations50