Inventor

KULKARNI JAYDEEP P

US33 patents

⚠️ This page may combine multiple inventors who share the name “KULKARNI JAYDEEP P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KULKARNI JAYDEEP P

INTEL CORP

Digitally trimmable integrated resistors including resistive memory elements

Voltage level shifter circuit

Assist circuit for memory

Reduced swing bit-line apparatus and method

Low swing bitline for sensing arrays

Apparatus for reducing write minimum supply voltage for memory

Voltage level shifter monitor with tunable voltage level shifter replica circuit

Capacitive wordline boosting

Voltage level shifter circuit

Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks

Aging aware dynamic keeper apparatus and associated method

Apparatus and method for reducing di/dt

Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks

Low swing bitline for sensing arrays

Apparatus for charge recovery during low power mode

Digitally trimmable integrated resistors including resistive memory elements

Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks

Resilient register file circuit for dynamic variation tolerance and method of operating the same

Apparatus and method for reducing di/dt during power wake-up

Assist circuit for memory

System, apparatus and method for reducing voltage swing on an interconnect

Current steering level shifter

KULKARNI JAYDEEP P

Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks

Apparatus for reducing write minimum supply voltage for memory

Circuits and methods for memory

Memory write operation methods and circuits

Resilient register file circuit for dynamic variation tolerance and method of operating the same

PURDUE RESEARCH FOUNDATION

Memory cell with built-in process variation tolerance

Static random access memory cell and devices using same

MEINERZHAGEN PASCAL A

Apparatus for dual purpose charge pump

RAYCHOWDHURY ARIJIT

Multi-supply sequential logic unit

NASRULLAH JAWAD

Methods and systems for energy efficiency and energy conservation including entry and exit latency reduction for low power states

WILKERSON CHRISTOPHER B

Adaptive self-repairing cache