Inventor

TIAN XINMIN

US39 patents

⚠️ This page may combine multiple inventors who share the name “TIAN XINMIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TIAN XINMIN

INTEL CORP

Thread-data affinity optimization using compiler

Method and apparatus for exploiting thread-level parallelism

Safe store for speculative helper threads

Programmable event driven yield mechanism which may activate other threads

Methods and apparatuses for thread management of multi-threading

Fast lock-free post-wait synchronization for exploiting parallelism on multi-core processors

Methods and apparatus for reducing memory latency in a software application

Systems and methods for cache optimization

Graphics processing unit processing and caching improvements

Method, system, and program of a compiler to parallelize source code

Mechanism for instruction set based thread execution of a plurality of instruction sequencers

System, method and apparatus for dependency chain processing

Systems and methods for cache optimization

Systems and methods for cache optimization

Programmable event driven yield mechanism which may activate other threads

Programmable event driven yield mechanism which may activate other threads

Apparatus, systems, and methods for execution-driven loop splitting and load-safe code hosting

Graphics processing unit processing and caching improvements

Graphics processing unit processing and caching improvements

Systems and methods for error detection and control for embedded memory and compute elements

Programmable event driven yield mechanism which may activate other threads

Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention

Methods, systems and apparatus to improve FPGA pipeline emulation efficiency on CPUs

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

Vectorize store instructions method and apparatus

Generating vector based selection control statements

Technologies for indirectly calling vector functions

WANG HONG

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

Programmable event driven yield mechanism which may activate other threads

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

LIAO SHIH-WEI

Compiler-based scheduling optimization hints for user-level threads

Methods and apparatuses for compiler-creating helper threads for multi-threading

LIN JIN

Loop parallelization based on loop splitting or index array

Speculative region-level loop optimizations

WANG PERRY

Programming environment for heterogeneous processor resource integration

HANKINS RICHARD A

Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention

TIAN XINMIN

Vectorization of scalar functions including vectorization annotations and vectorized function signatures matching

KRISHNAIYER RAKESH

Speculative compilation to generate advice messages

COWNIE JAMES H

Device, system, and method of executing a call to a routine within a transaction