Inventor
PREVITI-KELLY ROSEMARY A
US31 patents
⚠️ This page may combine multiple inventors who share the name “PREVITI-KELLY ROSEMARY A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
29 patentsUS5326430AJul 5, 1994
Cooling microfan arrangements and process
IBM174 citations99
US5219788AJun 15, 1993
Bilayer metallization cap for photolithography
IBM425 citations97
US5126006AJun 30, 1992
Plural level chip masking
IBM133 citations97
US5296775AMar 22, 1994
Cooling microfan arrangements and process
IBM66 citations96
US5194928AMar 16, 1993
Passivation of metal in metal/polyimide structure
IBM99 citations96
US5091289AFeb 25, 1992
Process for forming multi-level coplanar conductor/insulator films employing photosensitive polyimide polymer compositions
IBM56 citations96
US5043789AAug 27, 1991
Planarizing silsesquioxane copolymer coating
IBM54 citations96
US6495917B1Dec 17, 2002
Method and structure of column interconnect
IBM71 citations95
US5466636ANov 14, 1995
Method of forming borderless contacts using a removable mandrel
IBM63 citations95
US4723978AFeb 9, 1988
Method for a plasma-treated polysiloxane coating
IBM73 citations95
US5397741AMar 14, 1995
Process for metallized vias in polyimide
IBM48 citations94
US6458630B1Oct 1, 2002
Antifuse for use with low k dielectric foam insulators
IBM33 citations92
US5229257AJul 20, 1993
Process for forming multi-level coplanar conductor/insulator films employing photosensitive polymide polymer compositions
IBM22 citations92
US5114754AMay 19, 1992
Passivation of metal in metal/polyimide structures
IBM30 citations92
US4981530AJan 1, 1991
Planarizing ladder-type silsesquioxane polymer insulation layer
IBM43 citations92
US4606998AAug 19, 1986
Barrierless high-temperature lift-off process
IBM53 citations92
US5552638ASep 3, 1996
Metallized vias in polyimide
IBM33 citations90
US7144490B2Dec 5, 2006
Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layer
IBM14 citations84
US6452265B1Sep 17, 2002
Multi-chip module utilizing a nonconductive material surrounding the chips that has a similar coefficient of thermal expansion
IBM16 citations84
US6496053B1Dec 17, 2002
Corrosion insensitive fusible link using capacitance sensing for semiconductor devices
IBM17 citations83
US5503961AApr 2, 1996
Process for forming multilayer lift-off structures
IBM15 citations81
US6335229B1Jan 1, 2002
Inductive fuse for semiconductor device
IBM11 citations74
US5006488AApr 9, 1991
High temperature lift-off process
IBM12 citations74
US5451655ASep 19, 1995
Process for making thermostable coating materials
IBM7 citations73
US5286572AFeb 15, 1994
Planarizing ladder-type silsequioxane polymer insulation layer
IBM18 citations73
US6713838B2Mar 30, 2004
Inductive fuse for semiconductor device
IBM3 citations63
US5166038ANov 24, 1992
Etch resistant pattern formation via interfacial silylation process
IBM2 citations56
US6455434B1Sep 24, 2002
Prevention of slurry build-up within wafer topography during polishing
IBM2 citations55
US6835973B2Dec 28, 2004
Antifuse for use with low κ dielectric foam insulators
IBM0 citations52