Inventor

JOHNSON WILLIAM M

US104 patents

⚠️ This page may combine multiple inventors who share the name “JOHNSON WILLIAM M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JOHNSON WILLIAM M

ADVANCED MICRO DEVICES INC

High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations

System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache

Multiple instruction decoder for minimizing register port requirements

Processor configured to selectively cancel instructions from its pipeline responsive to a predicted-taken short forward branch instruction

Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments

Programmable cache memory as well as system incorporating same and method of operating programmable cache memory

Streamlined instruction processor

Direct memory access apparatus and methods for transferring data between buses having different performance characteristics

Instruction decoder/dispatch

Method of operating a high performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations

High performance superscalar microprocessor including a circuit for converting CISC instructions to RISC operations

Microprocessor arranged for synchronously accessing an external memory with a scalable clocking mechanism

Microprocessor arranged to synchronously access an external memory operating at a slower rate than the microproccessor

High performance superscalar microprocessor including a speculative instruction queue for byte-aligning CISC instructions stored in a variable byte-length format

High performance superscalar microprocessor including a dual-pathway circuit for converting cisc instructions to risc operations

High performance superscalar microprocessor including a circuit for byte-aligning cisc instructions stored in a variable byte-length format

Processing system for providing an in circuit emulator with processor internal state

Data transfer controller incorporating direct memory access channels and address mapped input/output windows

Input/output controller incorporating address mapped input/output windows and read ahead/write behind capabilities

High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure

Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor

Plural operand buses of intermediate widths coupling to narrower width integer and wider width floating point superscalar processing core

Superscalar microprocessor including a reorder buffer which detects dependencies between accesses to a pair of caches

Microprocessor configured to swap operands in order to minimize dependency checking logic

High performance superscalar microprocessor including an instruction cache circuit for byte-aligning CISC instructions stored in a variable byte-length format

Processing system with improved sequential memory accessing

Methods and apparatus for providing a user oriented microprocessor test interface for a complex, single chip, general purpose central processing unit

High performance load/store functional unit and data cache

Method for transferring data between a pair of caches configured to be accessed from different stages of an instruction processing pipeline

High performance load/store functional unit and data cache

Prefetch buffer for storing instructions prior to placing the instructions in an instruction cache

High speed instruction alignment unit for aligning variable byte-length instructions according to predecode information in a superscalar microprocessor

Reduced instruction set computer system including apparatus and method for coupling a high performance RISC interface to a peripheral bus having different performance characteristics

Exception handling processor for handling first and second level exceptions with reduced exception latency

General-purpose register file optimized for intraprocedural register allocation, procedure calls, and multitasking performance

IBM

Bidirectional serial test bus device adapted for control processing unit using parallel information transfer bus

Data processing system emulation with microprocessor in place

Processor including fetch operation for branch instruction with control tag

Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage

DRAPER LAB CHARLES S

Apparatus and method for autonomous satellite attitude sensing

Ballistic missile boresight and inertial tracking system and method

Common optical aperture laser separator for reciprocal path optical

JOHNSON WILLIAM M

Pad for a shoulder strap

Bicycle reflector for handlebar attachment

Bicycle reflector safety device

MCKAY RALPH LTD

Agricultural implement

Agricultural sweep with planar intermediate section

Agricultural discs

CELOTEX CORP

Removable-tilt-out window construction

NICHOLS HOMESHIELD INC

Adjustable roller assembly for sliding doors