Inventor
SCHEFFER LOUIS K
US32 patents
⚠️ This page may combine multiple inventors who share the name “SCHEFFER LOUIS K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CADENCE DESIGN SYSTEMS INC
20 patentsUS7231628B2Jun 12, 2007
Method and system for context-specific mask inspection
CADENCE DESIGN SYSTEMS INC314 citations98
US7712064B2May 4, 2010
Manufacturing aware design of integrated circuit layouts
CADENCE DESIGN SYSTEMS INC21 citations93
US7474999B2Jan 6, 2009
Method for accounting for process variation in the design of integrated circuits
CADENCE DESIGN SYSTEMS INC27 citations92
US7249342B2Jul 24, 2007
Method and system for context-specific mask writing
CADENCE DESIGN SYSTEMS INC37 citations92
US6543041B1Apr 1, 2003
Method and apparatus for reducing signal integrity and reliability problems in ICS through netlist changes during placement
CADENCE DESIGN SYSTEMS INC46 citations92
US6529913B1Mar 4, 2003
Database for electronic design automation applications
CADENCE DESIGN SYSTEMS INC42 citations90
US7024638B2Apr 4, 2006
Method for creating patterns for producing integrated circuits
CADENCE DESIGN SYSTEMS INC21 citations88
US8020135B2Sep 13, 2011
Manufacturing aware design and design aware manufacturing of an integrated circuit
CADENCE DESIGN SYSTEMS INC11 citations84
US7962866B2Jun 14, 2011
Method, system, and computer program product for determining three-dimensional feature characteristics in electronic designs
CADENCE DESIGN SYSTEMS INC7 citations84
US7827519B2Nov 2, 2010
Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs
CADENCE DESIGN SYSTEMS INC14 citations84
US7814447B2Oct 12, 2010
Supplant design rules in electronic designs
CADENCE DESIGN SYSTEMS INC8 citations84
US7721237B2May 18, 2010
Method, system, and computer program product for timing closure in electronic designs
CADENCE DESIGN SYSTEMS INC11 citations84
US7533359B2May 12, 2009
Method and system for chip design using physically appropriate component models and extraction
CADENCE DESIGN SYSTEMS INC17 citations84
US7395516B2Jul 1, 2008
Manufacturing aware design and design aware manufacturing
CADENCE DESIGN SYSTEMS INC10 citations84
US7254798B2Aug 7, 2007
Method and apparatus for designing integrated circuit layouts
CADENCE DESIGN SYSTEMS INC11 citations84
US7082588B2Jul 25, 2006
Method and apparatus for designing integrated circuit layouts
CADENCE DESIGN SYSTEMS INC18 citations84
US7627847B1Dec 1, 2009
Method and system for representing manufacturing and lithography information for IC routing
CADENCE DESIGN SYSTEMS INC7 citations74
US7784016B2Aug 24, 2010
Method and system for context-specific mask writing
CADENCE DESIGN SYSTEMS INC7 citations73
US7937674B2May 3, 2011
Method, system, and computer program product for predicting thin film integrity, manufacturability, reliability, and performance in electronic designs
CADENCE DESIGN SYSTEMS INC6 citations63
US7546562B1Jun 9, 2009
Physical integrated circuit design with uncertain design conditions
CADENCE DESIGN SYSTEMS INC6 citations63
SCHEFFER LOUIS K
5 patentsUS8136056B2Mar 13, 2012
Method and system for incorporation of patterns and design rule checking
SCHEFFER LOUIS K15 citations83
US8769453B2Jul 1, 2014
Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs
SCHEFFER LOUIS K4 citations72
US8713484B2Apr 29, 2014
Aware manufacturing of integrated circuits
SCHEFFER LOUIS K5 citations72
US8201128B2Jun 12, 2012
Method and apparatus for approximating diagonal lines in placement
SCHEFFER LOUIS K2 citations62
US8103982B2Jan 24, 2012
System and method for statistical design rule checking
SCHEFFER LOUIS K3 citations62