Inventor
SENGLE EDWARD W
US8 patents
Patents
8 patentsUS6624031B2Sep 23, 2003
Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure
IBM62 citations96
US6147394ANov 14, 2000
Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby
IBM54 citations95
US5972570AOct 26, 1999
Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby
IBM38 citations92
US6394638B1May 28, 2002
Trench isolation for active areas and first level conductors
IBM19 citations91
US5734192AMar 31, 1998
Trench isolation for active areas and first level conductors
IBM29 citations91
US7132325B2Nov 7, 2006
Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure
IBM10 citations73
US6770907B2Aug 3, 2004
Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure
IBM5 citations73
US6063687AMay 16, 2000
Formation of trench isolation for active areas and first level conductors
IBM0 citations50