Inventor
DAI WEI-JIN
US10 patents
⚠️ This page may combine multiple inventors who share the name “DAI WEI-JIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CADENCE DESIGN SYSTEMS INC
4 patentsUS6782519B2Aug 24, 2004
Clock tree synthesis for mixed domain clocks
CADENCE DESIGN SYSTEMS INC36 citations92
US6751786B2Jun 15, 2004
Clock tree synthesis for a hierarchically partitioned IC layout
CADENCE DESIGN SYSTEMS INC41 citations91
US6651235B2Nov 18, 2003
Scalable, partitioning integrated circuit layout system
CADENCE DESIGN SYSTEMS INC52 citations91
US6782520B1Aug 24, 2004
IC layout system having separate trial and detailed routing phases
CADENCE DESIGN SYSTEMS INC50 citations90
SILICON PERSPECTIVE CORP
3 patentsUS6249902B1Jun 19, 2001
Design hierarchy-based placement
SILICON PERSPECTIVE CORP451 citations95
US6519749B1Feb 11, 2003
Integrated circuit partitioning placement and routing system
SILICON PERSPECTIVE CORP60 citations93
US6578183B2Jun 10, 2003
Method for generating a partitioned IC layout
SILICON PERSPECTIVE CORP36 citations90
QUICKTURN DESIGN SYSTEMS INC
2 patentsUS5452239ASep 19, 1995
Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system
QUICKTURN DESIGN SYSTEMS INC436 citations94
US5886904AMar 23, 1999
Latch optimization in hardware logic emulation systems
QUICKTURN DESIGN SYSTEMS INC23 citations86