Inventor

MIZUSHIMA ICHIRO

JP103 patents

⚠️ This page may combine multiple inventors who share the name “MIZUSHIMA ICHIRO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MIZUSHIMA ICHIRO

TOSHIBA KK

Manufacturing method of partial SOI wafer, semiconductor device using the partial SOI wafer and manufacturing method thereof

Semiconductor substrate having pillars within a closed empty space

Semiconductor chip which combines bulk and SOI regions and separates same with plural isolation regions

Semiconductor device and method for manufacturing the same

Semiconductor device and method of manufacturing the same

Semiconductor device with oxide mediated epitaxial layer

Semiconductor device and manufacturing method thereof

Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor

Semiconductor device with a cavity therein and a method of manufacturing the same

Method of making empty space in silicon

Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer

Method of manufacturing a semiconductor device with oxide mediated epitaxial layer

Method of deforming a trench by a thermal treatment

Semiconductor device with element isolation film

Semiconductor device and manufacturing method thereof

Method for fabricating a localize SOI in bulk silicon substrate including changing first trenches formed in the substrate into unclosed empty space by applying heat treatment

Semiconductor chip which combines bulk and SOI regions and separates same with plural isolation regions

Semiconductor chip having multiple functional blocks integrated in a single chip and method for fabricating the same

Semiconductor device and manufacturing method thereof

Method of purging semiconductor manufacturing apparatus and method of manufacturing semiconductor device

Semiconductor device and manufacturing method thereof

Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor

Method and equipment for manufacturing semiconductor device

Semiconductor device and method of manufacturing the same

Semiconductor device having one of patterned SOI and SON structure

Semiconductor integrated circuit including insulated gate field effect transistor and method of manufacturing the same

Semiconductor device and semiconductor device manufacturing method

MIS-type semiconductor device having a multi-portion gate electrode

Semiconductor device and method of manufacturing same

Fin transistor

Nonvolatile semiconductor memory

Semiconductor device with recessed channel

Semiconductor device and manufacturing method thereof

Semiconductor memory device

Semiconductor device including MOSFET and isolation region for isolating the MOSFET

Semiconductor substrate, method of manufacturing the same, semiconductor device, and method of manufacturing the same

Semiconductor device and method of manufacturing the same including a dual layer raised source and drain

Non-volatile semiconductor memory

Semiconductor device comprises an impurity layer having boron ions in the form of clusters of icosahedron structure

Nonvolatile semiconductor memory

Semiconductor substrate, manufacturing method therefor, and semiconductor device

Element formation substrate for forming semiconductor device

Method for manufacturing partial SOI substrates

Semiconductor device and manufacturing method thereof

Semiconductor device comprising multiple layers with trenches formed on a semiconductor substrate

Semiconductor substrate having a partial SOI structure, method of manufacturing the same, a semiconductor device having a partial SOI structure, and method of manufacturing the same

MIZUSHIMA ICHIRO

Nonvolatile semiconductor memory device and method of fabricating the same

Nonvolatile semiconductor memory device and method of manufacturing the same

FUKUZUMI YOSHIAKI

Semiconductor memory device having a circuit formed on a single crystal semiconductor layer with varied germanium concentration

ICHIGE MASAYUKI

Nonvolatile semiconductor memory