Inventor

HINER DAVID JON

US67 patents

⚠️ This page may combine multiple inventors who share the name “HINER DAVID JON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HINER DAVID JON

AMKOR TECHNOLOGY INC

Semiconductor package including top-surface terminals for mounting another semiconductor package

Buildup dielectric and metallization process and semiconductor package

Method of manufacturing a semiconductor package

Buildup dielectric layer having metallization pattern semiconductor package fabrication method

Stacked embedded leadframe

Integrated circuit substrate having laser-exposed terminals

Semiconductor package including top-surface terminals for mounting another semiconductor package

Integrated circuit substrate having laminated laser-embedded circuit layers

Embedded leadframe semiconductor package

Semiconductor package with high routing density patch

Semiconductor device package and manufacturing method thereof

Substrate having stiffener fabrication method

Method for making an integrated circuit substrate having embedded back-side access conductors and vias

Semiconductor package and substrate having multi-level vias fabrication method

Semiconductor package and substrate having multi-level vias

Embedded electronic component package fabrication method

Direct-write wafer level chip scale package

Embedded metal features structure

Semiconductor device package and manufacturing method thereof

Semiconductor package with high routing density patch

Encapsulated semiconductor package

Semiconductor device package and manufacturing method thereof

Semiconductor device package and manufacturing method thereof

Semiconductor device package and manufacturing method thereof

Buildup dielectric layer having metallization pattern semiconductor package fabrication method

Semiconductor device package and manufacturing method thereof

Semiconductor device package formed in a chip-on-wafer last process using thin film adhesives

Through via connected backside embedded circuit features structure and method

Embedded die in panel method and structure

Method and structure for creating embedded metal features

Integrated circuit having multiple power/ground connections to a single external terminal

HINER DAVID JON

Method and system for backside dielectric patterning for wafer warpage and stress control

Through via connected backside embedded circuit features structure and method

Through via recessed reveal structure and method

Semiconductor package including top-surface terminals for mounting another semiconductor package

Extended landing pad substrate package structure and method

Method for making an integrated circuit substrate having laminated laser-embedded circuit layers

Trace stacking structure and method

HUEMOELLER RONALD PATRICK

Shielded embedded electronic component substrate fabrication method and structure

Multi-level circuit substrate fabrication method

Through via nub reveal method and structure

Embedded component package and fabrication method

Backside warpage control structure and fabrication method

AMKOR TECH SINGAPORE HOLDING PTE LTD

Semiconductor package with routing patch and conductive interconnection structures laterally displaced from routing patch

Semiconductor device package and manufacturing method thereof

Semiconductor package with high routing density patch

BERRY CHRISTOPHER JOHN

Direct-write wafer level chip scale package

Direct-write wafer level chip scale package

KELLY MICHAEL G

Method and system for a semiconductor for device package with a die-to-packaging substrate first bond

Method and system for a semiconductor device package with a die to interposer wafer first bond