Inventor
XEKALAKIS POLYCHRONIS
US17 patents
⚠️ This page may combine multiple inventors who share the name “XEKALAKIS POLYCHRONIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
14 patentsUS10324724B2Jun 18, 2019
Hardware apparatuses and methods to fuse instructions
INTEL CORP7 citations81
US9612840B2Apr 4, 2017
Method and apparatus for implementing a dynamic out-of-order processor pipeline
INTEL CORP3 citations71
US10409763B2Sep 10, 2019
Apparatus and method for efficiently implementing a processor pipeline
INTEL CORP6 citations70
US10338927B2Jul 2, 2019
Method and apparatus for implementing a dynamic out-of-order processor pipeline
INTEL CORP1 citations61
US12248785B2Mar 11, 2025
Instruction length decoding
INTEL CORP0 citations56
US10545735B2Jan 28, 2020
Apparatus and method for efficient call/return emulation using a dual return stack buffer
INTEL CORP0 citations50
US9823938B2Nov 21, 2017
Providing deterministic, reproducible, and random sampling in a processor
INTEL CORP1 citations50
US9817642B2Nov 14, 2017
Apparatus and method for efficient call/return emulation using a dual return stack buffer
INTEL CORP1 citations50
US9710389B2Jul 18, 2017
Method and apparatus for memory aliasing detection in an out-of-order instruction execution platform
INTEL CORP0 citations49
US10795681B2Oct 6, 2020
Instruction length decoding
INTEL CORP0 citations45
US10635465B2Apr 28, 2020
Apparatuses and methods to prevent execution of a modified instruction
INTEL CORP0 citations40
US10061587B2Aug 28, 2018
Instruction and logic for bulk register reclamation
INTEL CORP0 citations40
US10387159B2Aug 20, 2019
Apparatus and method for architectural performance monitoring in binary translation systems
INTEL CORP0 citations38
US10157063B2Dec 18, 2018
Instruction and logic for optimization level aware branch prediction
INTEL CORP0 citations36