Inventor

YANOVER IGOR

IL40 patents

⚠️ This page may combine multiple inventors who share the name “YANOVER IGOR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YANOVER IGOR

INTEL CORP

Systems, methods, and apparatuses for tile matrix multiplication and accumulation

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for tile load

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for tile load, multiplication and accumulation

Systems, methods, and apparatuses for tile matrix multiplication and accumulation

Systems, methods, and apparatuses for matrix operations

Linear memory address transformation and management

Apparatuses, methods, and systems to precisely monitor memory store accesses

Apparatuses, methods, and systems to precisely monitor memory store accesses

Scatter using index array and finite state machine

Gather using index array and finite state machine

Gather using index array and finite state machine

Accelerator systems and methods for matrix operations

Method and apparatus for proactive throttling for improved power transitions in a processor core

Hardware for split data translation lookaside buffers

Apparatuses, methods, and systems toprecisely monitor memory store accesses

Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bits

Accelerating memory fault resolution by performing fast re-fetching

Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bits

Accelerating memory fault resolution by performing fast re-fetching

Apparatus and method for power virus protection in a processor

Apparatus and method for power virus protection in a processor

Restricted speculative execution mode to prevent observable side effects

Adjusting a throttling threshold in a processor

Adjusting a throttling threshold in a processor

Method and apparatus to protect a processor against excessive power usage

Memory tagging apparatus and method

Memory tagging metadata manipulation

Memory tagging apparatus and method

Method and apparatus for memory aliasing detection in an out-of-order instruction execution platform

Apparatus and method for store pairing with reduced hardware requirements

Increasing invalid to modified protocol occurrences in a computing system

Instruction and logic for register based hardware memory renaming

SPERBER ZEEV

Gather using index array and finite state machine

Scatter using index array and finite state machine

SHALEV RON

Methods and apparatus for efficient communication between caches in hierarchical caching design

BAIR MICHAEL S

Regulating atomic memory operations to prevent denial of service attack